MC68EC060RC50 Freescale Semiconductor, MC68EC060RC50 Datasheet - Page 204

• Manufacturer Part Number: MC68EC060RC50
• Description: IC MPU 32BIT 50MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC50

• Processor Type: M680x0 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 50MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

The processor retries any read or write bus cycles of a read-modify-write sequence sepa-
rately; LOCK remains asserted during the entire retry sequence. If the last bus cycle of a
locked access is retried, LOCKE remains asserted through the retry of the write bus cycle.
When in the MC68040 acknowledge termination mode, a retry termination on the initial long-
word transfer of a line access causes the processor to retry the bus cycle as illustrated in
Figure 7-40. However, the processor interprets a retry bus operation signaled during the
second, third, or fourth long-word transfer of a line burst bus cycle as a bus error and causes
the processor to abort the line transfer. However, when in the native-MC68060 acknowledge
termination mode, a retry termination signaled during the second, third, or fourth long-word
transfers of a line burst bus cycle are ignored.
MOTOROLA
Figure 7-38. Line Read Access Bus Cycle Terminated with TEA Timing
MISCELLANEOUS
ATTRIBUTES
SIZ1–SIZ0
D31–D0
A31–A4
A1–A0
A3–A2
BCLK
R/W
TEA
SAS
CLA
TIP
TBI
TA
TS
C1
M68060 USER’S MANUAL
01
C2
C3
10
C4
11
TEA ENDS BURST—
NO EXCEPTION
TAKEN
Bus Operation
7-49