MC68EC060RC50 Freescale Semiconductor, MC68EC060RC50 Datasheet - Page 74

• Manufacturer Part Number: MC68EC060RC50
• Description: IC MPU 32BIT 50MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC50

• Processor Type: M680x0 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 50MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

FITC—1/2-Cache Mode (Instruction ATC)
DCO—Default Cache Mode (Data Cache)
DUO—Default UPA bits (Data Cache)
DWO—Default Write Protect (Data Cache)
DCI—Default Cache Mode (Instruction Cache)
DUI—Default UPA Bits (Instruction Cache)
Bit 0—Reserved by Motorola. Always read as zero.
MOTOROLA
These bits are two user-defined bits for operand accesses (see 4.2.2.3 Descriptor Field
Definitions ).
These bits are two user-defined bits for instruction prefetch bus cycles (see 4.2.2.3
Descriptor Field Definitions )
0 = The instruction ATC operates with 64 entries.
1 = The instruction ATC operates with 32 entries.
00 = Writethrough, cachable
01 = Copyback, cachable
10 = Cache-inhibited, precise exception model
11 = Cache-inhibited, imprecise exception model
0 = Reads and writes are allowed.
1 = Reads are allowed, writes cause a protection exception.
00 = Writethrough, cachable
01 = Copyback, cachable
10 = Cache-inhibited, precise exception model
11 = Cache-inhibited, imprecise exception model
M68060 USER’S MANUAL
Memory Management Unit
4-5