MC68EC060RC50 Freescale Semiconductor, MC68EC060RC50 Datasheet - Page 90

• Manufacturer Part Number: MC68EC060RC50
• Description: IC MPU 32BIT 50MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC50

• Processor Type: M680x0 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 50MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

tion at any level. Page descriptors also contain a supervisor-only (S) bit that can limit access
to programs operating at the supervisor privilege level.
The protection mechanisms can be used individually or in any combination to protect:
4.2.6.1 SUPERVISOR AND USER TRANSLATION TABLES. One
supervisor and user address spaces from unauthorized accesses is to use separate super-
visor and user translation tables. Separate trees protect supervisor programs and data from
accesses by user programs and user programs and data from access by supervisor pro-
grams. Supervisor programs may access user space through the MOVES instruction. With
a user-space SFC/DFC, the MOVES access will be translated according to the user-mode
translation tables. This translation table can be common to all tasks. Figure 4-16 illustrates
separate translation tables for supervisor accesses and for two user tasks that share the
common supervisor space. Each user task has a translation table with unique mappings for
the logical addresses in its user address space.
MOTOROLA
• Supervisor address space from accesses by user programs.
• User address space from accesses by other user programs.
• Supervisor and user program spaces from write accesses (implicitly supported by
• One or more pages of memory from write accesses.
designating all memory pages used for program storage as write protected).
URP FOR TASK 'A'
URP FOR TASK 'B'
COMMON SRP
FOR TASK 'A'
FOR TASK 'B'
Figure 4-16. Translation Table Structure for Two Tasks
POINTER
M68060 USER’S MANUAL
SUPERVISOR A LEVEL TABLE
USER A LEVEL TABLE
USER A LEVEL TABLE
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•
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•
•
•
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Memory Management Unit
way
TRANSLATION
TABLE FOR
ACCESSES
TRANSLATION
TABLE FOR
TASK 'A'
TRANSLATION
TABLE FOR
TASK 'B'
ALL SUPERVISOR
of
protecting
4-21