MC68EC060RC50 Freescale Semiconductor, MC68EC060RC50 Datasheet - Page 235

• Manufacturer Part Number: MC68EC060RC50
• Description: IC MPU 32BIT 50MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC50

• Processor Type: M680x0 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 50MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Exception Processing
The third step is to save the current processor contents for all exceptions other than reset.
The processor creates one of four exception stack frame formats on the supervisor stack
and fills it with information appropriate for the type of exception. Other information can also
be stacked, depending on which exception is being processed and the state of the processor
prior to the exception. Figure 8-2 illustrates the general form of the exception stack frame.
15
12 11
0
SP
STATUS REGISTER
PROGRAM COUNTER
FORMAT
VECTOR OFFSET
ADDITIONAL PROCESSOR STATE INFORMATION
(2 OR 4 WORDS, IF NEEDED)
Figure 8-2. General Form of Exception Stack Frame
The last step involves the determination of the address of the first instruction of the excep-
tion handler and then passing control to the handler. The processor multiplies the vector
number by four to determine the exception vector offset. It adds the offset to the value stored
in the vector base register (VBR) to obtain the memory address of the exception vector.
Next, the processor loads the program counter (PC) (and the supervisor stack pointer (SSP)
for the reset exception) from the exception vector table entry with the address of the first
instruction of the exception handler. The processor then fetches this instruction and initiates
exception handling. At the conclusion of exception handling, the processor resumes normal
processing at the address in the PC.
The MC68060 is unique from earlier members of the family in that if an interrupt is pending
during exception processing, the exception processing for that interrupt is deferred until the
first instruction of the exception handler of the current exception is executed. This allows any
exception handler to mask interrupts by ensuring that the first instruction of the exception
handler is an SR write that raises the interrupt level.
Normally, the end of an exception handler contains an RTE instruction. When the processor
executes the RTE instruction, it examines the stack frame on top of the supervisor stack to
determine if it is a valid frame. If the processor determines that it is a valid frame, the SR and
PC fields are loaded from the exception frame and control is passed to the specified instruc-
tion address.
All exception vectors are located in the supervisor address space and are accessed using
data references. Only the initial reset vector is fixed in the processor’s memory map; once
initialization is complete, there are no fixed assignments. Since the VBR provides the base
address of the exception vector table, the exception vector table can be located anywhere
in memory; it can even be dynamically relocated for each task that an operating system exe-
cutes.
MOTOROLA
M68060 USER’S MANUAL
8-3