MC68030FE25C Freescale Semiconductor, MC68030FE25C Datasheet - Page 122

• Manufacturer Part Number: MC68030FE25C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: CQUAD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

4.2 A D D R E S S
MOTOROLA
The processor specifies a target address space for every bus cycle with the
function code signals according to the type of access required. In addition
to distinguishing between supervisor user and program/data, the processor
and the memory management unit can control accesses and translate ad-
dresses appropriately. Table 4-1 lists the types of accesses defined for the
The memory locations of user program and data accesses are not predefined.
A function code of $7 ([FC2: FC0] = 111) selects the CPU address space. This
this space to communicate with external devices for special purposes. For
the CPU space should be done with caution.
can identify special processor cycles, such as the interrupt acknowledge cycle,
MC68030 and the corresponding values of function codes FC0-FC2.
long words beginning at memory location zero in the supervisor program
space are used for processor initialization. No other memory locations are
explicitly defined by the MC68030.
is a special address space that does not contain instructions or operands but
example, all M68000 processors use the CPU space for interrupt acknowledge
cycles. The MC68020 and MC68030 also generate CPU space accesses for
breakpoint acknowledge and coprocessor operations.
Supervisor programs can use the MOVES instruction to access all address
spaces, including the user spaces and the CPU address space. Although the
Neither are the locations of supervisor data space. During reset, the first two
is reserved for special processor functions. The processor uses accesses in
MOVES instruction can be used to generate CPU space cycles, this may
interfere with proper system operation. Thus, the use of MOVES to access
S P A C E T Y P E S
~Address space 3 is reserved for user definition, while 0 and 4
are reserved for future use by Motorola.
FC2
0
0
0
0
1
1
1
1
Table 4-1. Address Space Encodings
MC68030 USER'S MANUAL
FCl
0
0
0
1
0
1
1
1
FC0
0
0
0
0
1
1
1
1
User Data Space
User Program Space
CPU Space
(Undefined, Reserved)~
(Undefined, Reserved)~
(Undefined, Reserved)~
Supervisor Data Space
Supervisor Program Space
Address Space
4-5
m