MC68030FE25C Freescale Semiconductor, MC68030FE25C Datasheet - Page 559
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MC68030FE25C
Manufacturer Part Number
MC68030FE25C
Description
IC MPU 32BIT ENHANCED 132-CQFP
Manufacturer
Freescale Semiconductor
Specifications of MC68030FE25C
Processor Type
M680x0 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-CQFP
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
CQUAD
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68030FE25C
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC68030FE25C
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
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12
12-34
to suppress early termination may be included as required by a particular
the output of (C) be valid before the rising edge of state $1 (see Equation
The late termination circuit is formed by the gates (D) and (E). If the current
to delay propagation of this output by the required number of clock periods.
cycles with CIOU-I = asserted, and all cycles that missed in the cache on the
in (C) latches the termination condition of the current bus cycle at the rising
edge of AS, and this status is used during the next cycle. Other conditions
system, but propagation delays must be carefully considered in order that
cycle is accessing a cachable location, as determined by the output of (C),
and a cache hit has not occurred (D), then the BERR and HALT signals are
driven low (E).
operating with no wait states. A provision for generating wait states may be
included by placing additional timing stages between (C) and the MC68030
previous cycle and were not accesses to noncachable locations. The flip-flop
12-3 of Table 12-2).
Note that the logic depicted in Figure 12-18 is designed to support a cache
IACTIVE HIGH)
(ACTIVE HIGH)
CACHE HIT
CACHE HIT
CLOUT
- -
R/W
FC2
FC1
ECO -
AS
Figure 12-18. Example Early Termination Control Circuit
-
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CPUSPACE
MC68030 USER'S MANUAL
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