MC68030FE25C Freescale Semiconductor, MC68030FE25C Datasheet - Page 22

• Manufacturer Part Number: MC68030FE25C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: CQUAD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

MOTOROLA
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Figure
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Simplified Table Search Flowchart ..........................................
Table Search Initialization Flowchart ........................ ..............
ATC Entry Creation Flowchart ...............................................
Short-Format Invalid Descriptor .............................................
Short-Format Indirect Descriptor ...........................................
Long-Format Indirect Descriptor ............................. ....... ........
Five-Level Table Search ........................................................
Example Translation Tree Using Contiguous Memory .............
Example Translation Tree Using Indirect Descriptors ...............
Example Translation Tree Using Shared Tables ......................
Example Translation Tree with Nonresident Tables.. ...............
Detailed Flowchart of M M U Table Search Operation ...............
Limit Check Procedure Flowchart ...........................................
Translation Control Register (TC) Format ................................
Transparent Translation Register (TT0 and TT1) Format ...........
Long-Format Early Termination Page Descriptor .....................
Long-Format Page Descriptor ................................................
Long-Format Invalid Descriptor ............... ..............................
Detailed Flowchart of Descriptor Fetch Operation ....................
Logical Address Map Using Function Code Lookup
Example Translation Tree Using Function Code Lookup ..........
Example Translation Tree Structure for Two Tasks ..................
Example Logical Address Map with Shared Supervisor and
Example Translation Tree Using S and WP Bits to Set
Root Pointer Register (CRP, SRP) Format ................................
M M U Status Register (MMUSR) Format .................................
M M U Status Interpretation - - PTEST Level 0 ..........................
Asynchronous Non-DMA M68000 Coprocessor Interface
Coprocessor Address Map in MC68030 CPU Space ................
Coprocessor Interface Register Set Map .................................
Coprocessor General Instruction Format (cpGEN) ...................
M M U Status Interpretation - - PTEST Level 7 ........................
F-Line Coprocessor Instruction Operation Word .....................
MC68030 CPU Space Address Encodings ...............................
User Address Spaces ........................................................
Protection ........................................................................
Signal Usage ...................................................................
LIST OF ILLUSTRATIONS (Continued)
MC68030 USER'S MANUAL
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