MC68030FE25C Freescale Semiconductor, MC68030FE25C Datasheet - Page 209

• Manufacturer Part Number: MC68030FE25C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: CQUAD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

7
7-48
7.3.4 Synchronous Read Cycle
the same sequence. STERM rather than DSACKx is asserted bythe addressed
S t a t e 11
A synchronous read cycle is terminated differently from an asynchronous
read cycle; otherwise, the cycles assert and respond to the same signals, in
external device to terminate a synchronous read cycle. Since STERM must
of the clock while AS is asserted, it does not need to be synchronized by the
processor. Only devices with 32-bit ports may assert STERM. STERM is also
used with the CBREQ and CBACK signals during burst mode operation. It
cycles as well. Therefore, a synchronous cycle terminated with STERM with
one wait cycle is a three-clock bus cycle. However, note that STERM is as-
serted one-half clock later than DSACKx would be for a similar asynchronous
cycle with zero wait cycles (also three clocks). Thus, if dynamic bus sizing is
cache design than is available with DSACKx for three-clock accesses.
word operations are similar. Figure 7-32 is a functional timing diagram of a
synchronous long-word read cycle.
meet the synchronous setup and hold times with respect to all rising edges
provides a two-clock (minimum) bus cycle for 32-bit ports and single-clock
(minimum) burst accesses, although wait states can be inserted for these
not needed, STERN can be used to provide more decision time in an external
Figure 7-31 is a flowchart of a synchronous long-word read cycle. Byte and
The processor negates AS and DS during $11. It holds the address and
cycle.
The external device keeps DSACKx asserted until it detects the negation
of AS or DS (whichever it detects first). The device must remove its data
the negation of AS or DS.
data valid during $11 to provide address hold time for memory systems.
R/W and FC0-FC2 also remain valid throughout $11.
If more than one write cycle is required, $6-$11 are repeated for each write
and negate DSACKx within approximately one clock period after sensing
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