MC68030FE25C Freescale Semiconductor, MC68030FE25C Datasheet - Page 405

• Manufacturer Part Number: MC68030FE25C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: CQUAD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

10
10-18
10.2.2.4 TRAP ON COPROCESSOR CONDITION.
10.2.2.4.1 Format.
10.2.2.3.2 Protocol.
the word following the operation word to the condition CIR. The main pro-
the main processor executes the next instruction in the instruction stream.
to determine the address of the next instruction. The scanPC must point to
the 16-bit displacement in the instruction stream when the destination ad-
tion instruction allows the programmer to initiate exception processing based
The MC68030 transfers the condition selector to the coprocessor by writing
cessor then reads the response CIR to determine its next action. The copro-
cessor can use a response primitive to request any services necessary to
evaluate the condition. If the coprocessor returns the true condition indicator,
decrements the low-order word of the register specified by bits [0-2] of the
decremented, the main processor executes the next instruction in the in-
struction stream. If the register does not contain minus one ( - 1 ) after being
decremented, the main processor branches to the destination address to
continue instruction execution.
The MC68030 adds the displacement to the scanPC (refer to 10.4.1 ScanPC)
dress is calculated.
on conditions related to the coprocessor operation.
dition instruction, denoted by the cpTRAPcc mnemonic.
I
l
If the coprocessor returns the false condition indicator, the main processor
F-line operation word. If this register contains minus one ( - 1 ) after being
15
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]
Figure 10-13. Trap On Coprocessor Condition (cpTRAPcc)
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Figure 10-13 shows the format of the trap on coprocessor con-
~
Figure 10-8 shows the protocol for the cpDBcc instructions.
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OPTIONAL C O ~ E F I N E D
{RESERVED)
1
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MC68030 USER'S MANUAL
CplO
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0
8
0
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EXTENSION WORDS
The trap on coprocessor condi-
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5
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CONDITION SELECTOR
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3
I OPMODE
2
MOTOROLA
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