MC68030FE25C Freescale Semiconductor, MC68030FE25C Datasheet - Page 152

• Manufacturer Part Number: MC68030FE25C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: CQUAD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

6.1.3.2 BURST MODE:FILLING.
MOTOROLA
CYCLE
the state of the cache (whether or not the write cycle hits), the state of the
WA bit in the CACR, and the conditions indicated by the MMU.
the entry fill operation but does not necessarily cause a bus error exception.
takes an exception if the execution unit attempts to use the instruction word(s).
If all bytes of a long word are cachable, CIIN must be negated for all bus
cycles required to fill the entry. If any byte is not cachable, CIIN must be
asserted for all corresponding bus cycles. The assertion of the CIIN signal
prevents the ~ caches from being updated during read cycles. Write cycles
(including the write portion of a read-modify-write cycle) ignore the assertion
of the CIIN signal and may cause the data cache to be altered, depending on
The occurrence of a bus error while attempting to load a cache entry aborts
the processor immediately takes a bus error exception. If the read cycle in
error is made only to fill the data cache (the data is not part of the target
operand), no exception occurs, but the corresponding entry is marked invalid.
control register. The data burst enable bit must be set to enable burst filling
of the data cache. Similarly, the instruction burst enable bit must be set to
the corresponding cache is enabled, the bus controller requests a burst mode
fill operation in either of these cases:
If the bus error occurs on a read cycle for a portion of the required operand
(not the remaining bytes of the cache entry) to be loaded into the data cache,
For the instruction cache, the processor marks the entry as invalid, but only
enable burst filling of the instruction cache. When burst filling is enabled and
LONG WORD
LONG WORD
• A read cycle for either the instruction or data cache misses due to the
• A read cycle tag matches, but all long words in the line are invalid.
SIZE
indexed tag not matching.
ADDRESS
$06
$08
Misaligned Long Word and 32-Bit DSACKx Port
Figure 6-10. Single Entry Mode Operation
$oo
MC68030 USER'S MANUAL
Burst mode filling is enabled by bits in the cache
$O4
b,
I
l
$08
b8 b9
I
IbA b O
- FIRST WORD OF OPERANO PLUS
$OC
- SECOND WORB OF OPERAND PLUS
REST OF ENTRY AT $04
REST OF ENTRY AT$08
COMMENT
6-15
6