MC68030FE25C Freescale Semiconductor, MC68030FE25C Datasheet - Page 269

• Manufacturer Part Number: MC68030FE25C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: CQUAD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

8
8-2
the type of exception. Other information may also be stacked, depending on
the exception. If the exception is an interrupt and the M bit of the status
The last step initiates execution of the exception handler. The processor
from the exception vector table in memory, After prefetching the first three
w o r d s to fill the instruction pipe, the processor resumes normal processing
to calculate the address of the exception vector. T h r o u g h o u t this section,
which exception is being processed and the state of the processor prior to
a second stack frame on the interrupt stack.
gram counter (and the interrupt stack pointer (ISP) for the reset exception)
at the address in the program counter. Table 8-1 contains a description of
all the exception vector offsets defined for the MC68030.
9vector numbers are given in decimal notation.
For all exceptions other than reset, the third step is to save the current
processor context. The processor creates an exception stack frame on the
active supervisor stack and fills it with context information appropriate for
register is set, the processor clears the M bit in the status register and builds
multiplies the vector n u m b e r by four to determine the exception vector offset.
It adds the offset to the value stored in the vector base register to obtain the
m e m o r y address of the exception vector. Next, the processor loads the pro-
(Refer to SECTION 10 COPROCESSOR INTERFACE DESCRIPTION for a com-
plete discussion of coprocessor exceptions.) For all other exceptions, internal
logic provides the vector number. This vector n u m b e r is used in the last step
Number(s)
Vector
11
12
13
14
15
10
8
9
Table 8-1. Exception Vector Assignments (Sheet 1 of 2)
Vector Offset
Hex
00C
01C
02C
03C
000
004
008
010
014
018
020
024
028
030
034
038
Space
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
SP
SP
MC68030
Address Error
Zero Divide
CHK, CHK2 Instruction
cpTRAPcc, TRAPcc, TRAPV Instructions
Trace
Line 1010 Emulator
Line 1111 Emulator
(Unassigned, Reserved)
Coprocessor Protocol Violation
Reset Initial Interrupt Stack Pointer
Reset Initial Program Counter
Bus Error
Illegal Instruction
Privilege Violation
Format Error
UninJtialized Interrupt
USER'S MANUAL
Assignment
MOTOROLA
Asserted
STATUS
Yes
Yes
Yes
Yes
Yes
No
N o
No
No
No
N o
No
No
m