MC68030FE25C Freescale Semiconductor, MC68030FE25C Datasheet - Page 423

• Manufacturer Part Number: MC68030FE25C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: CQUAD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

IO
10-36
10.4.3 Busy Primitive
This primitive uses the PC bit as previously described.
the coprocessor is concurrently executing a cpGEN instruction, the copro-
tempted to initiate earlier.
the main processor and the coprocessor. If DR=0, the direction of transfer
The busy response primitive causes the main processor to reinitiate a co-
and conditional categories. Figure 10-23 shows the format of the busy pri-
I' IPcl
Coprocessors that can operate concurrently with the main processor but
cannot buffer write operations to their command or condition CIR use the
with an instruction in the main processor. If the main processor attempts to
cessor can place the busy primitive in the response CIR. When the main
coprocessor must record the instruction address to support any possible
to concurrent coprocessor instruction execution is discussed in 10.5.1
is from the main processor to the coprocessor (main processor write). If
DR = 1, the direction of transfer is from the coprocessor to the main processor
(main processor read). If the operation indicated by a given response pri-
mitive does not involve an explicit operand transfer, the value of this bit
depends on the particular primitive encoding.
processor instruction. This primitive applies to instructions in the general
mitive.
busy primitive. A coprocessor may execute a cpGEN instruction concurrently
initiate an instruction in the general or conditional instruction category while
processor reads this primitive, it services pending interrupts (using a pre-
instruction exception stack frame, refer to Figure 10-41). The processor then
restarts the general or conditional coprocessor instruction that it had at-
ceeds with instruction stream execution once the coprocessor releases it, the
exception processing related to the instruction. Exception processing related
processsor-Detected Exceptions.
Bit [13], the DR bit, is the direction bit. It applies to operand transfers between
15
14
13
12
Figure 10-23. Busy Primitive Format
11
10101,101010101010101010101
M068030 USER'S MANUAL
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MOTOROLA
2
Co-
1
0