MC68030FE25C Freescale Semiconductor, MC68030FE25C Datasheet - Page 285

• Manufacturer Part Number: MC68030FE25C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: CQUAD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

8
8-18
To predict the instruction boundary during which a pending interrupt is pro-
terrupt and the assertion of STATUS must be examined. Figure 8-6 shows
two examples of interrupt recognition. The first assertion of STATUS after
the clock edge that caused IPEND to assert (as shown in example 1), STAT1
the interrupt is acknowledged at the boundary defined by STAT1. If IPEND
time.
The state of the IPEND signal is internally checked by the processor once per
the second instruction prefetch associated with exception processing. Figure
8-5 is a flowchart of the interrupt recognition and associated exception pro-
cessing sequence.
cessed, the timing relationship between the assertion of IPEND for that in-
IPEND is denoted as STAT0. The next assertion of STATUS is denoted as
STAT1. If STAT0 begins on the falling edge of the clock immediately following
is at least two clocks long, and, when there are no other pending exceptions,
is asserted with more setup time to STAT0, the interrupt may be acknowl-
edged at the boundary defined by STAT0 (as shown in example 2). In that
case, STAT0 is asserted for two clocks, signaling this condition.
INTERRUPT ACKNOWLEDGE CYCLE q TERMINATED NORMALLY),
instruction, independently of bus operation. In addition, it is checked during
If no higher priority interrupt has been synchronized, the IPEND signal is
negated during state 0 (SO) of an interrupt acknowledge cycle (refer to 7.4.1.1
IPLx signals for the interrupt being acknowledged can be negated at this
IPL0-1PL2
IP~s RECOGNI Z ED - ~
I P END
CLN
S Y N C H R O N I Z E D
X
C O M P A R E REQUEST
WITH MASK IN SR
Ks
Figure 8-4. Assertion of IPEND
MC68030 USER'S MANUAL
ASSERT IPEND
MOTOROLA
and the