MC68030FE25C Freescale Semiconductor, MC68030FE25C Datasheet - Page 128

• Manufacturer Part Number: MC68030FE25C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: CQUAD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

MOTOROLA
Cache Burst Request
A u t o v e c t o r
Data Transfer and
Synchronous
Cache Inhibit In
Cache Inhibit Out
Cache Burst
Interrupt Priority Level
Interrupt Pending
Bus Grant Acknowledge
Reset
Halt
Cache Disable
Clock
Power Supply
Ground
Bus Request
BUS Grant
Bus Error
MMU Disable
Pipe Refill
Microsequencer Status
Acknowledge
Size Acknowledge
Termination
Signal Name
Table 5-1. Signal Index (Sheet 2 of 2)
Mnemonic
IPLO-IPL2
DSACK0
MMUDIS
DSACK1
STATUS
STERM
BGACK
CBREQ
CBACK
CLOUT
RESET
REFILL
IPEND
AVEC
MC68030 USER'S MANUAL
HALT
BERR
CDIS
GND
VCC
ClIN
CLK
m
BR
BG
Bus response signals that indicate the requested data trans-
fer oceration is completed. In addition, these two lines in-
dica:e :he size of the external bus port on a cycle-by-cycle
basis anc are used for asynchronous transfers.
that data may
Prevents data from being loaded into the MC68030 instruc-
tion and data caches.
Reflects the CI bit in ATC entries or TTx register; indicates
that external caches should ignore these accesses.
Provides an encoded interrupt level to the processor.
cycle.
ship.
ship.
System reset.
tempted.
Dynamically disables the on-chip cache to assist emulator
support.
Clock input to the processor.
Power supply.
Ground connection.
Bus response signal that indicates a port size of 32 bits and
Indicates a burst request for the instruction or data cache.
Indicates that the accessed device can operate in burst mode.
Indicates that an interrupt is pending.
Requests an autovector during an interrupt acknowledge
Indicates that an external device requires bus mastership.
Indicates that an external device may assume bus master-
Indicates that an external device has assumed bus master-
Indicates that the processor should suspend bus activity.
Indicates that an erroneous bus operation is being at-
Dynamically disables the translation mechanism of the MMU.
Indicates when the MC68030 is beginning to fill pipeline.
Indicates the state of the microsequencer.
be latched
Function
on the next
falling clock edge.
5-3
: - 5