MC68030FE25C Freescale Semiconductor, MC68030FE25C Datasheet - Page 467

• Manufacturer Part Number: MC68030FE25C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: CQUAD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

1
11.2.3 Instruction Cache
11.2.4 Data Cache
11.2.5 Bus Controller Resources
11-4
the instruction cache, and the bus controller. Thus, even if the instruction
The instruction cache services the instruction prefetch portion of the micro-
sequencer. The prefetch of an instruction that hits in the on-chip instruction
cache causes no delay in instruction execution since no external bus activity
The data cache services data reads and is updated on data writes. Data
cache cause no delay in instruction execution due to external bus activity for
the data fetch. The data cache also interacts with the external bus during
data cache fills following data cache misses.
to be performed. Similarly, when data reads miss in the on-chip data cache,
The bus controller and microsequencer can operate on an instruction con-
accessed from the instruction cache or the external bus and loaded into the
cache holding register, and the high-order word is also loaded into stage B
of the pipe. The instruction word for the next sequential prefetch can then
cycle or instruction cache access is required. The cache holding register
cache is enabled or disabled.
Prefetch requests are simultaneously submitted to the cache holding register,
cache is disabled, an instruction prefetch may hit in the cache holding register
and cause an external bus cycle to be aborted.
is required for the prefetch. The instruction cache also interacts with the
external bus during instruction cache fills following instruction cache misses.
operands required by the execution unit that are accessed from the data
Prefetches that miss in the instruction cache cause an external memory cycle
an external memory cycle is required. The time required for either of these
bus cycles may be overlapped with other internal activity.
currently. The bus controller can perform a read or write while the micro-
sequencer controls an effective address calculation or sets the condition
quests an even-word (long-word aligned) prefetch, the entire long word is
be accessed directly from the cache holding register, and no external bus
provides instruction words to the pipe, regardless of whether the instruction
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