MC68030FE25C Freescale Semiconductor, MC68030FE25C Datasheet - Page 257

• Manufacturer Part Number: MC68030FE25C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: CQUAD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

7
7-96
7.7 B U S A R B I T R A T I O N
the bus controller in the MC68030 manages the bus arbitration signals so
that the processor has the lowest priority. External devices that need to obtain
the bus must assert the bus arbitration signals in the sequences described
The bus design of the MC68030 provides for a single bus master at any one
time: either the processor or an external device. One or more of the external
devices on the bus can have the capability of becoming bus master. Bus
arbitration is the protocol by which an external device becomes bus master;
when two or more external devices attempt to become bus master at the
same time, the one having the highest priority becomes bus master first. The
sequence of the protocol is:
ternal decision to execute a bus cycle. Then, the assertion of BG is deferred
in the following paragraphs, Systems having several devices that can become
bus master require external circuitry to assign priorities to the device so that,
BR may be issued any time during a bus cycle or between cycles. BG is
asserted in response to BR; it is usually asserted as soon as BR has been
synchronized and recognized, except when the MC68030 has made an in-
until the bus cycle has begun. Additionally, BG is not asserted until the end
of a read-modify-write operation (when RMC is negated) in response to a BR
3. The external device asserts the bus grant acknowledge signal to indicate
2. The processor asserts the bus grant signal to indicate that the bus will
1. An external device asserts the bus request signal.
that it has assumed bus mastership.
become available at the end of the current bus cycle.
Figure 7-58. Bus Synchronization Example
MOVE L DO.(AO)
WRITE TO O. CACHE
SO
MC68030 USER'S MANUAL
~ f
m
EXTERNAL WRITE
Sw
O. CACHE READ
NOP PREVENTS EXECUTION OF SUBSEQUENT
INSTRUCTIONS UNTIL MOVEL DO,(AO)
WRITE CYCLE COMPLETES
MOVE.L (AO).O1
X
MOTOROLA