MC68030FE25C Freescale Semiconductor, MC68030FE25C Datasheet - Page 416

• Manufacturer Part Number: MC68030FE25C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: CQUAD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

MOTOROLA
10.3
10.3.1 Response CIR
COPROCESSOR INTERFACE REGISTER SET
receives the invalid format code, writes an abort mask (refer to 10.2.3.2.3
the restore CIR and terminates any current operations. The main processor
The cpRESTORE instruction is a privileged instruction. When the main pro-
violation exception processing without accessing any of the coprocessor
to the coprocessor's programming model.
the response CIR is $00. Refer to 10.4 COPROCESSOR RESPONSE PRIMI-
TIVES.
coprocessor state frame, the coprocessor places an invalid format word in
Invalid Format Word) to the control CIR, and initiates format error exception
cessor accesses a cpRESTORE instruction, it checks the supervisor bit in the
status register. If the MC68030 attempts to execute a cpRESTORE instruction
while at the user privilege level (status register bit [13] = 0), it initiates privilege
The instructions of the M68000 coprocessor interface use registers of the CIR
set to communicate with the coprocessor. These CIRs are not directly related
defined for the M68000 coprocessor interface.
The following paragraphs contain detailed descriptions of the registers.
The coprocessor uses the 16-bit response CIR to communicate all service
If the format word written to the restore CIR does not represent a valid
processing (refer to 10.5.1.5 FORMAT ERRORS).
interface registers (refer to 10.5.2.3 PRIVILEGE VIOLATIONS).
Figure 10-4 is a memory map ofthe CIR set. The registers denoted by asterisks
(*) must be included in a coprocessor interface that implements coprocessor
instructions in all four categories. The complete register model must be
implemented if the system uses all of the coprocessor response primitives
requests (coprocessor response primitives) to the main processor. The main
processor reads the response CIR to receive the coprocessor response pri-
mitives during the execution of instructions in the general and conditional
instruction categories. The offset from the base address of the CIR set for
MC68030 USER'S MANUAL
10-29
10