MC68030FE25C Freescale Semiconductor, MC68030FE25C Datasheet - Page 190

• Manufacturer Part Number: MC68030FE25C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: CQUAD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

7.2.10 Synchronous Operation with STERM
MOTOROLA
The MC68030 supports synchronous bus cycles terminated with STERM.
These cycles, for 32-bit ports only, are similar to cycles terminated with
trolled by the assertion of STERM, and wait cycles can be inserted as nec-
To assure proper operation in a synchronous system when BERR or BERR
and HALT is asserted after DSACKx, BERR (and HALT) must meet the ap-
clock cycle after DSACKx is recognized. This setup time is critical, and the
When operating synchronously, the data-in setup and hold times for syn-
chronous cycles may be used instead of the timing requirements for data
The value of CIIN is latched on the rising edge of bus cycle state 4 for all
cycles terminated with DSACKx.
DSACKx. The main difference is that STERM can be asserted (and data can
be transferred) earlier than for a cycle terminated with DSACKx, causing the
processor to perform a minimum access time transfer in two clock periods.
However, wait cycles can be inserted by delaying the assertion of STERM
appropriately.
Using STERM instead of DSACKx in any bus cycle makes the cycle synchron-
ous. Any bus cycle is synchronous if:
cycles. The first cycle of any burst transfer must be a synchronous cycle as
described in the preceding paragraph. The exact timing of this cycle is con-
essary. However, the minimum cycle time is two clocks. If a burst operation
cycles latch data on successive falling edges of the clock at a minimum.
Again, the exact timing for these subsequent cycles is controlled bythe timing
of STERM for each of these cycles, and wait cycles can be inserted as nec-
propriate setup time (parameter #27A) prior to the falling clock edge one
MC68030 may exhibit erratic behavior if it is violated.
relative to the DS signal.
Burst mode operation requires the use of STERM to terminate each of its
is initiated and allowed to terminate normally, the second, third, and fourth
essary.
3. Synchronous input setup and hold time requirements (specifications
2. The port size is 32 bits.
1. Neither DSACKx nor AVEC is recognized during the cycle.
#60 and #61) for STERM are met.
MC68030 USER'S MANUAL
7-29
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