MC68030FE25C Freescale Semiconductor, MC68030FE25C Datasheet - Page 546

• Manufacturer Part Number: MC68030FE25C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: CQUAD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

MOTOROLA
The second section contains the memory devices. Eight devices are used,
for lower power consumption, the timing in this design will be preserved if
the memory's E signal is asserted before the falling edge of state SO (at the
The third section of the memory bank is the data buffers. The data buffers
write memory bank. The required parts include:
density. The most important feature of the memory devices used in this
design is the separate data-in and data-out pins, which allow the SRAMs to
contention. The enable pins on the SRAMs have been grounded for both
simplicity and .improved memory access timing. If the designer wishes to
same time as or before the address becomes valid). Two possible enable
circuits are shown in Figure 12-11.
are shown as 74F244, but 74AS244s may also be used. The RDCS signal,
qualified with AS, controls the data buffers during read operations as de-
scribed above.
To maximize performance, both read and write operations should be capable
of completing in two clock cycles. Figure 12-12 shows a two-clock read and
but some designs may wish to increase this to support EDAC or to increase
be enabled before address decode is complete without causing data bus
include some type of enable circuitry to take advantage of low bus utilization
(4)
(1)
(8)
(2)
(1)
(1)
(2)
(1)
vcc
ECS - -
74F244 buffers
74F32 OR gates
74F74 D-type flip-flop
74F373 transparent latches
74AS21 AND gate
74F04 inverter
PAL16L8D (or equivalent)
AS
16K×4 SRAMs, 25-ns access time with separate I/O pins
Figure 12-11. Additional Memory Enable Circuits
CLK[
VCC
p
74F74
MC68030 USER'S MANUAL
TERM
ECS - -
CLK
0
CLK[
VCC
g
74F74
12-21
12