MC68030FE25C Freescale Semiconductor, MC68030FE25C Datasheet - Page 565

• Manufacturer Part Number: MC68030FE25C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: CQUAD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

12
12-40
translation process performed by the on-chip MMU, creating a local address
The MC68030 begins an external cycle by driving the address bus and as-
chip cache memories cannot be captured externally since the cache access
does not depend on the availability of the external bus.
AS, RESET, STATUS, REFILL, STERM, and ECS) are connected to the MC68030
to aid in capturing and analyzing data. In addition to connecting the logic
trace interface signals (SAMPLE, PHALT, FILL, EP, IE, and ECSC) should also
when the SAMPLE signal is high. Table 12-5 lists the parts required to im-
execution.
The pipelined architecture of the MC68030 prefetches instructions and op-
erands to keep the three stages of the instruction pipe full. The pipeline allows
concurrent operations to occur for up to three words of a single instruction
or for up to three consecutive instructions. While sequential instruction ex-
ecution is the norm, it is possible that prefetched data is not used by the
execution unit due to a nonsequential event. The STATUS signal allows trace
hardware to mark the progress of the execution unit as it processes program
memory operands and allows marking of some exceptions. Nonsequential
events, where the entire pipeline needs to reload before continuing execution,
are marked by the REFILL signal.
External hardware typically has no visibility into on-chip cache memory op-
erations. However, the MC68030 provides a local address reference to in-
crease visibility. Write operations are totally visible since the MC68030
implements a writethrough policy allowing external hardware to capture
data. For read operations from on-chip cache memories, the least significant
byte of the address bus provides a local address reference.
serting the external cycle start (ECS) signal. Address strobe (AS) asserts later
in the cycle to validate the address. If a hit occurs in the cache or the cache
holding register, then the external cycle is aborted and AS is not asserted.
In addition, the low-order address bits (A0-A7) are not involved in the address
reference which can be used by trace functions. All read cycles from the on-
Figure 12-23 shows a trace interface circuit which can be used with a logic
analyzer for program debug. The nine input signals (DSACK1, DSACK0, CLK,
processor in the system under development. Six output signals are generated
analyzer to the address bus, the data bus, and the bus control signals, the
system CLK signal for synchronization. Setting up the logic analyzer for data
capture requires that samples be taken on the falling edge of the CLK signal
plement this circuit.
piing signal when valid data is present on the bus. This allows for tracing
data flow in and out of the processor, which is the basis for tracking program
be connected. The external clock probe of the logic analyzer connects to the
MC68030 USER'S MANUAL
MOTOROLA