MC68030RC40C Freescale Semiconductor, MC68030RC40C Datasheet - Page 103

• Manufacturer Part Number: MC68030RC40C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC40C

• Processor Type: M680x0 32-Bit
• Speed: 40MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 40MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

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3.4 INSTRUCTION SET SUMMARY
Table 3-14 provides a alphabetized listing of the MC68030 instruction set
Table 3-14 use notational conventions for the operands, the subfields and
qualifiers, and the operations performed by the instructions. In the syntax
Table 3-14.
listed by opcode, operation, and syntax.
descriptions, the left operand is the source operand, and the right operand
is the destination operand. The following list contains the notations used in
Notation for operands:
Notation for subfields and qualifiers:
(<address register>) +--Location of the instruction operand - - t h e op-
-(<address register>)--Indicates that the operand register points to the
<bit> of <operand>--Selects a single bit of the operand
(<address register>)--The register indirect operator
<ea>{offset:width}--Selects a bit field
#xxx or #<data>--Immediate data that follows the instruction
Immediate Data--Immediate data from the instruction
<operand>lO--The operand is binary coded decimal, operations
(<operand>)--The contents of the referenced location
Destination--Destination contents
Source--Source contents
<fmt>--Operand data format: byte (B), word (W), long
Vector--Location of exception vector
+ inf--Positive infinity
-
FPm--One of eight floating-point data registers (always
FPn--One of eight floating-point data registers (always
SR--Status register
PC--Program counter
inf--Negative infinity
M C 6 8 0 3 0 U S E R ' S M A N U A L
V--Overflow condition code
tional, mode qualifiers are - , +, (d), and (d,ix)
word(s)
specifies the source register)
specifies the detination register)
a r e
memory
(L), single (S), double (D), extended (X), or packed
(P).
performed in decimal
M O T O R O L A