MC68030RC40C Freescale Semiconductor, MC68030RC40C Datasheet - Page 421

• Manufacturer Part Number: MC68030RC40C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC40C

• Processor Type: M680x0 32-Bit
• Speed: 40MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 40MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

10
10-34
10.4.1 ScanPC
following the coprocessor command word. For the cpBcc instructions, the
word following the coprocessor condition specifier word.
with a general or conditional instruction, the coprocessor must use these
words consistently so that the scanPC is updated accordingly during the
These paragraphs describe the scanPC and tell how it operates.
the MC68030 contains the address of the F-line operation word of that in-
struction. A second register, called the scanPC, sequentially addresses the
dress or destination address of a branch operation, it uses the scanPC to
address these extension words in the instruction stream. Also, if a copro-
cessor requests the transfer of extension words, the scanPC addresses the
extension words during the transfer. As the processor references each word,
When an instruction is completed, the processor transfers the value in the
scanPC to the program counter to address the operation word of the next
The value in the scanPC when the main processor reads the first response
scanPC points to the word following the instruction F-line operation word.
of any coprocessor-defined extension words in the instruction format.
Several of the response primitives involve the scanPC, and many of them
During the execution of a coprocessor instruction, the program counter in
remaining words of the instruction.
If the main processor requires extension words to calculate an effective ad-
it increments the scanPC to point to the next word in the instruction stream.
instruction.
primitive after beginning to execute an instruction depends on the instruction
being executed. For a cpGEN instruction, the scanPC points to the word
For the cpScc, cpTRAPcc, and cpDBcc instructions, the scanPC points to the
If a coprocessor implementation uses optional instruction extension words
instruction execution. Specifically, during the execution of general category
instructions, when the coprocessor terminates the instruction protocol, the
MC68030 assumes that the scanPC is pointing to the operation word of the
next instruction to be executed. During the execution of conditional category
instructions, when the coprocessor terminates the instruction protocol, the
MC68030 assumes that the scanPC is pointing to the word following the last
require the main processor to use it while performing services requested.
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