MC68030RC40C Freescale Semiconductor, MC68030RC40C Datasheet - Page 491

• Manufacturer Part Number: MC68030RC40C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC40C

• Processor Type: M680x0 32-Bit
• Speed: 40MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 40MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

1
1 1-28
11.6.2
t o calculate and fetch the specified destination operand. In the case of two-
The fetch immediate effective address table indicates the number of clock
word instructions, this table indicates the number of clock periods needed
for the processor to fetch the second word of the instruction and to calculate
and fetch the specified source operand or single operand. The effective ad-
dresses are divided by their formats (refer to 2.5 Effective Address Encoding
Summary). For instruction-cache case and for no-cache case, the total num-
and write cycles is given inside the parentheses as (r/p/w). The read, prefetch,
and write cycles are included in the total clock cycle number.
All timing data assumes two-clock reads and writes.
I
I
periods needed for the processor to fetch the immediate source operand and
ber of clock cycles is outside the parentheses. The number of read, prefetch,
SINGLE EFFECTIVE ADDRESS INSTRUCTION FORMAT
% #(dataXW,Dn
% #(data~.L,Dn
BRIEF FORMAT EXTENSION WORD
Fetch I m m e d i a t e Effective A d d r e s s (flea)
#<data).W,(An)
#(data).L,(An)
#(data).W,(An) +
#(data>.L,(An) +
#<data>.W, - (An)
#(data).L,- (An)
#<data).W,$XXX.W
#(data).L,$XXX.W
#(data).W,(d16, An)
#(data).L,(d16,An)
#(data).W,$XXX.L
#(data>.L,$XXX.L
#(data~.W,#<data~.L
#(data).L,(d8,An,Xn) or (d8,PC,Xn)
#(data).W,(d8,An,Xn) or (ds,PC,Xn)
Addre,,Mode
MC68030 USER'S M A N U A L
I
4+op
2+op
6+op
4
.earl
2
2
2
2
4
4
6
3
5
1
1
head
head
head
I Ta,
I ,-Cao,eCa,e I No-Cao,eCa.I
10(1/0/0)
2(01010)
4(01010)
3(11010)
4(11010)
5(1/0/0)
7(1/0/0)
4(1/0/0)
4(1/0/0)
4(1/0/0)
6(1/0/0)
6(11010)
8(1/0/0)
6(1/0/0)
8(1/0/0)
6(0/0/0)
8(11010)
I
M O T O R O L A
10(1/2/0)
2(01110)
4(0/1/0)
5(11110)
5(11110)
4(111/0)
6(11110)
5(11110)
8(112/0)
7(11210)
9(11210)
6(01210)
8(1121o)
4(11110)
6(11110)
7(1/1/0)
8(1/2/0)