MC68030RC40C Freescale Semiconductor, MC68030RC40C Datasheet - Page 213

• Manufacturer Part Number: MC68030RC40C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC40C

• Processor Type: M680x0 32-Bit
• Speed: 40MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 40MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

7
7-52
State 0
State 1
functional timing diagram of this operation with wait states.
of STERM for any two-clock synchronous bus cycle. The system must qualify
a memory write with the assertion of AS to ensure that the write is not aborted
Figure
by internal conditions within the MC68030.
I
The write cycle starts with S0. The processor drives ECS low, indicating
the beginning of an external cycle. When the cycle is the first cycle of a
write operation, OCS is driven low at the same time. During SO, the pro-
10) ASSERT DATA STROBE (' O ' S ) (IF WAIT STATES)
cessor places a valid address on A0"A31 and valid function codes on
dicating the number of bytes to be transferred. CLOUT also becomes valid,
or in the appropriate TTx register.
One-half clock later in $1, the processor asserts AS, indicating that the
address on the address bus is valid. The processor also asserts DBEN
during Sl, which may be used to enable the external data buffers. In ad-
dition, the ECS (and OCS, if asserted) signal is negated during Sl.
FC0-FC2. The function codes select the address space for the cycle. The
processor drives R/W low for a write cycle. SIZ0-SIZ1 become valid, in-
indicating the state of the MMU CI bit in the address translation descriptor
9) DRIVE DATA LINES DO-D31
3) NEGATE OBEN
1} ASSERT ECS/OCS FOR ONE-HALF CLOCK
2) DRIVE ADDRESS ON AO-A31
3) DRIVE FUNCTION CODE ON FCO-FC2
4) DRIVE SIZE (SIZO-SIZ1) (FOUR BYTES)
5) SET R/WTO WRITE
6} CACHE INHIBIT OUT (CLOUT) BECOMES VALID
7) ASSERT ADDRESS STROBE (~)
8} ASSERT DATA BUFFER ENABLE (DBEN)
2) REMOVE DATA FROM DO-D31
1) NEGATE ~(AND ~)"
7-33 is a
TERMINATE OUTPUT TRANSFER
START NEXT DYCLE
Figure 7-33. Synchronous Write Cycle Flowchart
ADDRESS DEVICE
PROCESSOR
flowchart of a synchronous write cycle. Figure
MC68030 USER'S MANUAL
I
j
2) STORE DATA FROM DO-D31
3} ASSERT SYNCHRONOUS TERMINATION (STERM)
1) NEGATE STERM
1) DECODE ADDRESS
TERMINATE CYCLE
ACCEPT DATA
EXTERNAL DEVICE
MOTOROLA
7-34 is a