MC68030RC40C Freescale Semiconductor, MC68030RC40C Datasheet - Page 166

• Manufacturer Part Number: MC68030RC40C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC40C

• Processor Type: M680x0 32-Bit
• Speed: 40MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 40MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

7.1.5 Data Strobe
7.1.4
7.1.6 Data Buffer Enable
7.1.7
MOTOROLA
The data bus signals (D0-D31) comprise a bidirectional, nonmultiplexed par-
A read or write operation may transfer 8, l & 24, or 32 bits of data (one, two,
three, or four bytes) in one bus cycle. During a read cycle, the data is latched
width or operand size. The processor places the data on the data bus one-
The data strobe (DS) is a timing signal that applies to the data bus. For a
The data buffer enable signal (DBEN) can be used to enable external data
to terminate the bus cycle and to latch the data. During a write cycle, the
the data and that the cycle may terminate. These signals also indicate to the
allel bus that contains the data being transferred to or from the processor.
by the processor on the last falling edge of the clock for that bus cycle. For
a write cycle, all 32 bits of the data bus are driven, regardless of the port
half clock cycle after AS is asserted in a write cycle.
read cycle, the processor asserts DS to signal the external device to place
data on the bus. It is asserted at the same time as AS during a read cycle.
For a write cycle, D-S signals to the external device that the data to be written
is valid on the bus. The processor asserts DS one full clock cycle after the
assertion of AS during a write cycle.
buffers while data is present on the data bus. During a read operation, DBEN
as DS is negated. In a write operation, DBEN is asserted at the time AS is
asserted and is held active for the duration of the cycle. In a synchronous
system supporting two-clock bus cycles, DBEN timing may prevent its use.
and size acknowledge signals (DSACK0 and/or DSACK1) as part of the bus
protocol. During a read cycle, the assertion of DSACKx signals the processor
assertion of DSACKx indicates that the external device has successfully stored
processor the size of the port for the bus cycle just completed, as shown in
Table 7-1. Refer to 7.3.1
of DSACK0 and DSACK1.
is asserted one clock cycle after the beginning of the bus cycle and is negated
During asynchronous bus cycles, external devices assert the data transfer
Data Bus
Bus Cycle Termination Signals
MC68030 USER'S MANUAL
Asynchronous Read Cycle
for timing relationships
7-5
7