MC68030RC40C Freescale Semiconductor, MC68030RC40C Datasheet - Page 283

• Manufacturer Part Number: MC68030RC40C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC40C

• Processor Type: M680x0 32-Bit
• Speed: 40MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 40MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

8
8-16
transition sensitive. The processor recognizes an interrupt request each time
When several devices are connected to the same interrupt level, each device
Table 8-4 lists the interrupt levels, the states of IPL2-1PLO that define each
the external interrupt request level
7, regardless of the value in the mask. Figure 8-3 shows two examples of
with a value of 6 before entering the handler routine so that subsequent level
the MC68030 is handling a level 7 interrupt (status register mask set tO 7)
terrupt is also generated by a level comparison if the request level and mask
should hold its interrupt priority level constant until its corresponding inter-
rupt acknowledge cycle to ensure that all requests are processed.
level, and the mask value that allows an interrupt at each level.
Priority level 7, the nonmaskable interrupt (NMI), is a special case. Level 7
interrupts cannot be masked by the interrupt priority mask, and they are
interrupt recognitions, one for level 6 and one for level 7. When the MC68030
processes a level 6 interrupt, the status register mask is automatically updated
6 interrupts are masked. Provided no instruction that lowers the mask value
is executed, the external request can be lowered to level 3 and then raised
back to level 6 and a second level 6 interrupt is not processed. However, if
and the external request is lowered to level 3 and than raised back to level
7, a second level 7 interrupt is processed. The second level 7 interrupt is
processed because the level 7 interrupt is transition sensitive. A level 7 in-
level are at seven and the priority mask is then set to a lower level (with the
MOVE to SR or RTE instruction, for example). As shown in Figure 8-3 for
level 6 interrupt request level and mask level, this is the case for all interrupt
levels.
*Indicates that no interrupt is requested.
Interrupt Level
Requested
0*
2
4
1
3
5
6
7
Table 8-4. Interrupt Levels and Mask Values
MC68030 USER'S M A N U A L
High
High
High
High
Low
Low
Low
Low
IP2
Control Line Status
High
High
High
Low
Low
High
Low
IP1
Low
changes
High
High
High
High
Low
Low
Low
Low
IP0
from some lower level to level
Required for Recognition
Interrupt Mask Level
N/A*
0-1
0-2
0-3
0-4
0-5
0-7
0
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