MC68030RC40C Freescale Semiconductor, MC68030RC40C Datasheet - Page 198

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MC68030RC40C

Manufacturer Part Number
MC68030RC40C
Description
IC MPU 32BIT ENHANCED 128-PGA
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MC68030RC40C

Processor Type
M680x0 32-Bit
Speed
40MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
128-PGA
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
40MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Through Hole
Pin Count
128
Package Type
PGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant

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7.3.2 Asynchronous Write Cycle
MOTOROLA
two read cycles with no idle time) for a 32-bit port, Figure 7-26 shows byte
The following figures show the functional write cycle timing diagrams spec-
and word write cycles to a 32-bit port. Figure 7-27 shows a long-word write
cycle to an 8-bit port. Figure 7-28 shows a long-word write cycle to a 16-bit
During a write cycle, the processor transfers data to memory or a peripheral
device.
Figure 7-24 is a flowchart of a write cycle operation for a long-word transfer.
ified in terms of clock periods. Figure 7-25 shows two write cycles (between
port.
101 ASSERT DATA STROBE In]
2)
3) DRIVE FUNCTION CODE ON FCO-FC2
41 DRIVE SIZE {SIZO-SIZ1) (FOUR BYTES;
6) CACHE INHIBIT OUT rCIOUT) BECOMES VALID
1) ASSERT ECS/OCS FOR ONE-HALF CLOCK
St SET R/W TO WRITE
7) ASSERT ADDRESS STROBE (~)
8) ASSERT DATA BUFFER ENABLE (DBENI
9) DRIVE DATA LINES DO-D31
2) REMOVE DATA FROM 00-03'
3) NEGATE DBEN
I) NEGATE AS AND DS
DRIVE ADDRESS ON AO-A3]
TERMINATE OUTPUT TRANSFER
Figure 7-24. Asynchronous Write Cycle Flowchart
START NEXT CYCLE
AODRESS DEVICE
PROCESSOR
MC68030 USER'S MANUAL
2) STORE DATA FROM O0-D31
3) ASSERT DATA TRANSFER AND SIZE ACKNOWLEDGE ( ~ I
]) NEGATE OSAOKx
]~ DECODE ADDRESS
EXTERNAL DEVICE
TERMINATE CYCLE
ACCEPT DATA
7-37
IB

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