MC68030RC40C Freescale Semiconductor, MC68030RC40C Datasheet - Page 145

• Manufacturer Part Number: MC68030RC40C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC40C

• Processor Type: M680x0 32-Bit
• Speed: 40MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 40MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

6
6-8
6.1.2.1 WRITE ALLOCATION.
o f data that is not long word may invalidate a previously valid entry or entries.
for either of two types of allocation for data cache entries that miss on write
When no write allocation is selected (WA=0), write cycles that miss do not
When write allocation is selected (WA = 1 ), the processor always updates the
When a tag miss occurs on a write of long-word data that is long-word
aligned, the corresponding tag is replaced, and only the long word being
written is marked as valid. The other three entries in the cache line are
a byte or word write, the data is not written in the cache, the tag is unaltered,
and the valid bit(s) are cleared. Thus, an aligned long-word data write may
Write allocation eliminates stale data that may reside in the cache because
of either of two unique situations: multiple mapping of two or more logical
addresses to one physical address within the same task or allowing the same
Stale data conditions can arise when operating in the no-write-allocation
cycles. The state of the write allocation (WA) bit in the cache control register
specifies either no write allocation or write allocation with partial validation
of the data entries in the cache on writes.
alter the data cache contents. In this mode, the processor does not replace
entries in the cache during write operations. The cache is updated only during
a write hit.
data cache on cachable write cycles, but only validates an updated entry that
hits or an entry that is updated with long-word data that is long-word aligned.
invalidated when a tag miss occurs on a misaligned long-word write or on
replace a previously valid entry; whereas, a misaligned data write or a write
physical location to be accessed by both supervisor and user mode cycles.
mode and all the following conditions are satisfied:
• Multiple mapping (object aliasing) is allowed by the operating system.
• A read cycle loads a value for an "aliased" physical address into the
• The physical object is then read using the first alias, which provides stale
• A write cycle occurs, referencing the same aliased physical object as
data cache.
above but using a different logical address, causing a cache miss and
no update to the cache (has the same page offset).
data from the cache.
MC68030 USER'S MANUAL
The supervisor program can configure the data cache
MOTOROLA