MC68030RC40C Freescale Semiconductor, MC68030RC40C Datasheet - Page 455

• Manufacturer Part Number: MC68030RC40C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC40C

• Processor Type: M680x0 32-Bit
• Speed: 40MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 40MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

0
10-68
10.5.2.2 F-LINE EMULATOR EXCEPTIONS.
ceiving an invalid primitive, the main processor aborts the coprocessor in-
tected by the MC68030 are either explicitly or implicitly related to the en-
Also, an operation word with bits [8:6] =000-101 that does not map to one
to initiate F-line emulator exception processing. If the F-line emulator excep-
tion is either of these two situations, the main processor does not write to
the control CIR prior to initiating exception processing.
exceptions that can result from the use of the M68000 coprocessor response
to the control CIR prior to F-line emulator exception processing.
Another type of F-line emulator exception occurs when a bus error occurs
during the coprocessor interface register access that initiates a coprocessor
When the main processor initiates F-line emulator exception processing, it
ception handler does not modify the stack frame, the main processor attempts
to restart the instruction that caused the exception after it executes an RTE
The exception handler adjusts the program counter field of the saved stack
frame to point to the next instruction operation word and executes the RTE
tion that was emulated.
codings of F-line operation words in the instruction stream. If the main
out initiating any communication with the coprocessor for that instruction.
of the valid coprocessor instructions in the instruction set causes the MC68030
F-line exceptions can also occur if the operations requested by a coprocessor
response primitive are not compatible with the effective address type in bits
primitives are summarized in Table 10-6. If the exception is caused by re-
struction in progress by writing an abort mask (refer to 10.3.2 Control CIR)
instruction. The main processor assumes that the coprocessor is not present
and takes the exception.
uses the four-word pre-instruction exception stack frame (refer to Figure
instruction to return from the exception handler.
If the cause of the F-line exception can be emulated in software, the handler
stores the results of the emulation in the appropriate registers of the pro-
grammer's model and in the status register field of the saved stack frame.
processor determines that an F-line operation word is not valid, it initiates
F-line emulator exception processing. Any F-line operation word with bits
[8:6] = 110 or 111 causes the MC68030 to initiate exception processing with-
[0-5] of the coprocessor instruction operation word. The F-line emulator
10-41) and the F-line emulator exception vector number 11. Thus, if the ex-
instruction. The MC68030 then executes the instruction following the instruc-
MC68030 USER'S MANUAL
The F-line emulator exceptions de-
MOTOROLA