MC68030RC40C Freescale Semiconductor, MC68030RC40C Datasheet - Page 370

• Manufacturer Part Number: MC68030RC40C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC40C

• Processor Type: M680x0 32-Bit
• Speed: 40MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 40MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

9.9.3.2 INITIAL SHIFT COUNT.
MOTOROLA
t h e system performs on lists of data. These actions require the system to
the block sizes on available I/O devices, yet keep the tables manageable.
frequency of page faults requiring more table search time and paging I/O.
With the flexibility of the MC68030 MMU, the designer has enough choices
to optimize table structure design and page size.
Three-level translation tables are useful when the operating system makes
the page table level. When a table entry can point to a translation table also
with only small fragments of memory allocated among these widely differing
ory most efficiently. However, small pages in a large virtual memory map
virtual address space with 256-byte pages, the page tables alone require 64
translation table entries can be drastically reduced. The designer can use
fields in valid descriptors to minimize the sizes of pointer and page tables.
virtual address space can be addressed with fewer than 32 bits, the IS field
entries maps a 16-Mbyte region of the virtual address space. The primary
advantage of a two-level table for large "number-crunching" system is the
operating system designer's ability to make a tradeoff between page size
and table size. The system designer may choose a smaller page size to fit
However, the designer must also consider the performance penalty associ-
ated with smaller page sizes. Systems with smaller page sizes have a higher
heavy use of shared memory spaces and/or shared page tables. Sophisticated
systems often share translation tables or program and data areas defined at
used by a different task, sharing memory areas becomes efficient. The direct
access to user address space by the supervisor is an example of sharing
memory.
Some artificial intelligence systems require very large virtual address spaces
addresses. This fragmentation is due to the complex and recursive actions
constantly allocate and free sophisticated pointers and linked lists in the
memory map, The fragmentation suggests a small page size to utilize mem-
require relatively large translation tables. For example, to map 4 Gbytes of
invalid descriptors to represent blocks of unused addresses and the limit
In addition, paging of the address tables themselves reduces memory re-
quirements.
register (TC) can decrease the size of translation tables. When the required
reduces the size of the virtual address space by discarding the appropriate
number of the most significant logical address bits. This technique inhibits
Mbytes. With a three- or four-level table structure, the number of actual
MC68030 USER'S MANUAL
The initial shift field (IS) of the translation control
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