Z16C3516VSG Zilog, Z16C3516VSG Datasheet - Page 145

• Manufacturer Part Number: Z16C3516VSG
• Description: IC 16MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3516VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4690-5; Z16C3516VSG

UM011001-0601
Table 13 shows a “macro” to enable the Z180 to use the
Z80 Assembler, as well as register definitions.
There is one good test to ensure proper function. Generate
a data transfer between the Z180/SCC using the Z180 on-
;*
;*
;*
;
;Z180 System Control Registers
;ASCI Registers
cntla0:
cntla1:
cntlb0:
cntlb1:
stat0:
stat1:
tdr0:
tdr1:
rdr0:
rdr1:
;CSI/O Registers
cntr:
trdr:
;Timer Registers
tmdr0l:
tmdr0h:
rldr0l:
rldr0h:
tcr:
tmdr1l:
tmdr1h:
rldr1l:
rldr1h:
frc:
;DMA Registers
sar0l:
sar0h:
sar0b:
dar0l:
dar0h:
dar0b:
bcr0l:
bcr0h:
mar1l:
mar1h:
mar1b:
iar1l:
iar1h:
Macro library for Z180 new instructions for asm800
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
File name - 180macro.lib
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0ah
0bh
0ch
0dh
0eh
0fh
10h
14h
15h
16h
17h
18h
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2ah
2bh
2ch
Table 13. Program Example – Z180 CPU Macro Instructions
; ASCI Cont Reg A Ch0
; ASCI Cont Reg A Ch1
; ASCI Cont Reg B Ch0
; ASCI Cont Reg B Ch1
; ASCI Stat Reg Ch0
; ASCI Stat Reg Ch1
; ASCI Tx Data Reg Ch0
; ASCI Tx Data Reg Ch1
; ASCI Rx Data Reg Ch0
; ASCI Rx Data Reg Ch1
; CSI/O Cont Reg
; CSI/O Tx/Rx Data Reg
; Timer Data Reg Ch0-low
; Timer Data Reg Ch0-high
; Timer Reload Reg Ch0-low
; Timer Reload Reg Ch0-high
; Timer Cont Reg
; Timer Data reg Ch1-low
; Timer Data Reg Ch1-high
; Timer Reload Reg Ch1-low
; Timer Reload Reg Ch1-high
; Free Running Counter
; DMA Source Addr Reg Ch0-low
; DMA Source Addr Reg Ch0-high
; DMA Source Addr Reg Ch0-b
; DMA Dist Addr Reg Ch0-low
; DMA Dist Addr Reg Ch0-high
; DMA Dist Addr Reg Ch0-B
; DMA Byte Count Reg Ch0-low
; DMA Byte Count Reg Ch0-high
; DMA Memory Addr Reg Ch1-low
; DMA Memory Addr Reg Ch1-high
; DMA Memory Addr Reg Ch1-b
; DMA I/O Addr Reg Ch1-low
; DMA I/O Addr Reg Ch1-high
chip DMA. The SCC self loop-back test transfers data
using the Z180 DMA at the highest transmission rate
(Table 13).
The Z180™ Interfaced with the SCC at MHZ
Application Note
7-25
7