Z16C3516VSG Zilog, Z16C3516VSG Datasheet - Page 234

• Manufacturer Part Number: Z16C3516VSG
• Description: IC 16MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3516VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4690-5; Z16C3516VSG

Application Note
Technical Considerations When Implementing LocalTalk Link Access Protocol
APPENDIX A
Listing 1- Asembler Code for SCC Initialization
000001e2
000001e2 f3
000001e3 f5
000001e4 c5
000001e5 e5
000001e6 3e09
000001e8 d3e8
000001ea 3e80
000001ec d3e8
000001ee 00
000001ef 21Wwww
000001f2
000001f2 7e
000001f3 feff
000001f5 caWwww
000001f8 d3e8
000001fa 23
000001fb 7e
000001fc d3e8
000001fe 23
000001ff c3R000+01f2,
00000202
00000202 04
00000203 20
00000204 01
00000205 00
00000206 02
00000207 00
00000208 03
00000209 cc
0000020a 05
0000020b 60
0000020c 06
0000020d 00
0000020e 07
0000020f 7e
00000210 09
00000211 01
14-8
475
476
477
478 initscc:
479
480
481
482
483
484
485
486
487
488
489
490
491
492 scc1:
493
494
495
496
497
498
499
500
501
502
503 scctable:
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
di
push
push
push
ld
out
ld
out
nop
ld
ld
cp
jp
out
inc
ld
out
inc
jp
db
db
db
db
db
db
db
db
db
db
db
db
db
db
db
db
LISTING 1
af
bc
hl
a,09h
(scc_cont),a
a,80h
(scc_cont),a
hl,scctable
a,(hl)
0ffh
z,finscc
(scc_cont),a
hl
a,(hl)
(scc_cont),a
hl
scc1
04h
00100000b
01h
00h
02h
00h
03h
0cch
05h
60h
06h
00h
07h
7eh
09h
01h
;subroutine to initialize scc registers
;disable int while programming scc
;WR9
;point to scc register
;channel reset
;scc register value
;delay needed after scc reset
;fetch start of scc init table
;fetch register pointer value
;if reg a =0ffh then initscc finished
;loop back
;WR4
;sdlc uses 1x,sdlc mode,no parity
;WR1
;nothing,rx,tx and ext int disabled
;WR2
;vector base is 00h
;WR3
;rx 8b/char,rx crc enabled,address
;search mode for adlc address filtering
;rx disabled.
;WR5
;tx 8b/char, set rts to disable drivers
;WR6
;address field=’myaddress’ in main pgm
;WR7
;flag pattern
;WR9
;stat low, vis therefore vector returned
;is a variable depending on the source
;of the interrupt.
;***************************************
;***************************************
UM011001-0601