Z16C3516VSG Zilog, Z16C3516VSG Datasheet - Page 22

• Manufacturer Part Number: Z16C3516VSG
• Description: IC 16MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3516VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4690-5; Z16C3516VSG

Z16C35ISCC™ User’s Manual
ISCC™ DMA and Ancillary Support Circuitry
Receive Character Available bit in the SCC cell in Read
Register 0.
The SCC cell will not generate a DMA request in the case
of a special receive condition in the Receive Interrupt on
First Character or Special Condition mode, or the Receive
Interrupt on Special Condition Only mode.
In these two interrupt modes any receive character with a
special receive condition is locked at the top of the FIFO
until an Error Reset command is issued. This character in
the receive FIFO would ordinarily cause additional DMA
Requests after the first time it is read. However, the logic
in the SCC cell guarantees no extra DMA transfers by ter-
minating DMA requests after the time the character with
the special receive condition is read, and the FIFO locked.
DMA requests are held off until after the Error Reset com-
mand has been issued.
Once the FIFO is locked, it allows the checking of the Re-
ceive Error FIFO (RR1) to find the cause of the error. Lock-
ing the data FIFO therefore, will stop the error status from
popping out of the Receive Error FIFO. Also, since DMA
request will become inactive, the interrupt (Special Condi-
tion) can be serviced. Once the FIFO is unlocked by the
Error Reset command, DMA requests again follow the
state of the receive FIFO.
3.2.2 Transmitter DMA Operation
With the DMA enabled, the status of an empty transmitter
FIFO triggers the DMA to request the bus and begin DMA
transfer to the transmit FIFO. Once this DMA channel is
selected for service, DMA transfers continue until the
3.3 BAUD RATE GENERATOR
The Baud Rate Generator (BRG) is essential for asynchro-
nous communications. Each channel in the ISCC contains
a programmable baud rate generator. Each generator con-
sists of two 8-bit, time-constant registers forming a 16-bit
time constant, a 16-bit down counter, and a flip-flop on the
output that makes the output a square wave. On start-up,
the flip-flop on the output is set High, so that it starts in a
known state, the value in the time-constant register is load-
ed into the counter, and the counter begins counting down.
When a count of zero is reached, the output of the baud
rate generator toggles, the value in the time-constant reg-
ister is loaded into the counter, and the process starts
over. A block diagram of the baud rate generator is shown
in Figure 3-1.
The time-constant can be changed at any time, but the
new value does not take effect until the next load of the
counter (i.e., after zero count is reached).
No attempt is made to synchronize the loading of a new
time-constant with the clock used to drive the generator.
3-2
transmit FIFO is full (or until terminal count is reached if
there are not enough bytes remaining to fill the FIFO).
Once started, the DMA for the channel continues until the
FIFO is full even though a request from a higher priority
DMA channel arises. Upon completion of the current DMA
channel service, the next highest priority DMA channel
commences its operation. The ISCC continues to hold the
bus until all pending DMA requests have been served.
Note that if the Bus Request Per Channel option has been
selected, then the bus will be released and subsequently
re-requested for each channel. At the completion of the
block transfer (terminal count reached), an interrupt will be
generated, if enabled. If selected, the interrupt vector will
indicate the interrupt source according to Table 3-1.
An Interrupt Pending only modifies the interrupt vector if
the corresponding Interrupt Enable bit is set. Note that
software may have to test status bits to determine if the
channel interrupt is due to terminal count or an abort.
Note that the DMA request will follow the state of the trans-
mit FIFO even though the transmitter is disabled. Thus, if
the DMA is enabled, the DMA may write data to the SCC
cell before the transmitter is enabled. This will not cause a
problem in Asynchronous mode but may cause problems
in Synchronous mode because the ISCC will send data in
preference to flags or sync characters. Thus a data char-
acter in the transmit FIFO may get transmitted prior to the
frame sync character or opening flag. It may also compli-
cate the CRC initialization, which cannot be done until after
the transmitter is enabled. DMA requests essentially follow
the Tx Buffer Empty bit in the SCC cell Read Register 0.
When the time-constant is to be changed, the generator
should be stopped first by writing to an enable bit in WR14.
After loading the time constant, the BRG can be started
again. This ensures the loading of a correct time constant,
but loading will not be taking place until zero count or a re-
set occurs.
If neither the transmit clock nor the receive clock are pro-
grammed to come from the /TRxC pin, the output of the
baud rate generator may be made available for external
use on the /TRxC pin.
The clock source for the baud rate generator is selected by
bit D1 of WR14. When this bit is set to “0,” the baud rate
generator uses the signal on the /RTxC pin as its clock, in-
dependent of whether the /RTxC pin is a simple input or
part of the crystal oscillator circuit. When this bit is set to
“1,” the baud rate generator is clocked by PCLK. To avoid
metastable problems in the counter, this bit should be
changed only while the baud rate generator is disabled,
UM011001-0601