Z16C3516VSG Zilog, Z16C3516VSG Datasheet - Page 62

• Manufacturer Part Number: Z16C3516VSG
• Description: IC 16MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3516VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4690-5; Z16C3516VSG

Z16C35ISCC™ User’s Manual
Register Descriptions
5.2 REGISTER DESCRIPTIONS (Continued)
5.2.2 Read Registers, SCC Cell
Four read registers indicate status information, two are for
baud rate generation, and one for the receive buffer. In ad-
dition, there are two read registers which are shared by
both channels: one for the interrupt pending bits and one
for interrupt vector. See Table 5-2 for a summary on the
SCC cell read registers.
Register
RR0
RR1
RR2
RR3
RR6
RR7
RR8
RR10
RR12
RR13
RR15
5.2.3 DMA Registers
The DMA cell contains 16 read write registers for con-
trol of the DMA channels. The DMA possesses its own
interrupt vector register and interrupt control registers
which are independent of the SCC cell. The DMA cell
also includes the Bus Configuration Register (BCR) for
5.3 SCC CELL REGISTER OVERVIEW
The SCC cell write register set in each channel includes
ten control registers (among them is the transmit buffer),
two sync character registers and two baud rate time con-
stant registers. The interrupt control register and the mas-
ter interrupt control and reset register are shared by both
channels.
5-2
Table 5-2. SCC Cell Read Registers
Description
Transmit and Receive buffer status and
external status
Special Receive Condition status
Modified interrupt vector (Channel B only),
Unmodified
interrupt vector (Channel A only)
Interrupt pending bits (Channel A only)
SDLC FIFO byte counter lower byte (only
when enabled)
SDLC FIFO byte count and status (only when
enabled)
Receive buffer
Miscellaneous status bits
Lower byte of baud rate generator time
constant
Upper byte of baud rate generator time
constant
External Status interrupt information
P R E L I M I N A R Y
the ISCC. The addresses, names and descriptions of
these registers are given in Table 5-3.
Address
xxxxx
00000
00000
00001
00010
00011
00011
00100
00101
00110
00111
01000-01001 RDCRA Receive DMA Count Register
01010-01011 TDCRA Transmit DMA Count Register
01100-01101 RDCRB Receive DMA Count Register
01110-01111 TDCRB Transmit DMA Count Register
10000-10011 RDARA Receive DMA Address Register
10100-10111 TDARA Transmit DMA Address Register
11000-11011 RDARB Receive DMA Address Register
11100-11111 TDARB Transmit DMA Address Register
The only variation in register definition is between the mul-
tiplexed and non-multiplexed bus mode programming of
the ISCC. The variation exists in the command decode
structure; register WR0. The following sections describe in
detail each write register and the associated bit configura-
tion for each.
Table 5-3. DMA Cell Register Description
Name
BCR
CCAR
DSR
ICR
IVR
ICSR
ISR
DER
DCR
Description
Bus Configuration Register
Channel Command/Address
Register (Write)
DMA Status Register (Read)
Interrupt Control Register
Interrupt Vector Register
Interrupt Command Register
(Write)
Interrupt Status Register (Read)
DMA Enable/Disable Register
DMA Control Register
Reserved Address
Reserved Address
Channel A (Low-high byte)
Channel A
Channel B
Channel B
Channel A
Channel A
Channel B
Channel B
UM011001-0601