Z16C3516VSG Zilog, Z16C3516VSG Datasheet - Page 242

• Manufacturer Part Number: Z16C3516VSG
• Description: IC 16MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3516VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4690-5; Z16C3516VSG

Application Note
Technical Considerations When Implementing LocalTalk Link Access Protocol
00000509
00000509 f5
0000050a c5
0000050b e5
0000050c 21Wwww
0000050f 7e
00000510 cbcf
00000512 77
00000513 e1
00000514 c1
00000515 f1
00000516 fb
00000517 ed4d
00000a00
00000a00
00000a00
00000a08 R000+03e9,
00000a0a R000+04c8,
00000a0c R000+0433,
00000a0e R000+0454,
00000a10
00000a18
00000ad0
00000ad0 R000+04d8,
00000ad2
00000ad2 R000+0509,
14-8
1306
1307
1308
1309
1310 ctc1int:
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338 sccvect:
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351 temp:
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
push
push
push
ld
ld
set
ld
pop
pop
pop
ei
reti
org
if
.block
endif
dw
dw
dw
dw
if
.block
endif
.block
org
dw
org
dw
LISTING 4
af
bc
hl
hl,timflg
a,(hl)
1,a
(hl),a
hl
bc
af
sdlc + 0a00h
scc_a
8
txint
ext_stat
recint
spcond
not scc_a
8
1
0ad0h
ctc0int
0ad2h
ctc1int
;****************************************
;ctc1 timer int handler
;****************************************
;ctc1 is programmed in counter mode.
;external trigger edges is provided by
;/trxc pin at intervals of 4.3 usec.
;bit1 of timflg is set when count is terminated.
;** update the timing flag **
;get recent timflg
;bit1=1 after count is over
;update the timflg
;**********************************
;interrupt vector table for the scc
;**********************************
;the status of the interrupt source will affect
;the interrupt vector. The interrupt handler’s
;address are set in a block, as below.
;reserve vector for other ch
;tx int
;ext/stat int
;rx char int
;sp rec cond int
;reserve vector for other ch
;**********************************
;interrupt vector table for the ctc
;**********************************
;reserved for ctc0 int routine
;reserved for ctc1 int routine
;************************
;receive buffer area
;************************
UM011001-0601