Z16C3516VSG Zilog, Z16C3516VSG Datasheet - Page 26

• Manufacturer Part Number: Z16C3516VSG
• Description: IC 16MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3516VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4690-5; Z16C3516VSG

Z16C35ISCC™ User’s Manual
ISCC™ DMA and Ancillary Support Circuitry
3.5 DIGITAL PHASE-LOCKED LOOP (DPLL)
Each channel of the SCC cell contains a digital phase-
locked loop that can be used to recover clock information
from a data stream with NRZI, FM or NRZ encoding. The
DPLL is driven by a clock nominally 32 (NRZI) or 16 (FM)
times the data rate. The DPLL uses this clock, along with
the data stream, to construct a receive clock for the data.
This clock can then be used as the ISCC receive clock, the
transmit clock, or both.
The clock for the DPLL is selected by two of the com-
mands in WR14, that is:
The first command selects the baud rate generator as the
clock source. The other command selects /RTxC pin as
the clock source, independent of whether the /RTxC pin is
a simple input or part of the crystal oscillator circuit.
Initialization of the DPLL may be done at any time during
the initialization sequence, but should preferably be done
after the clock modes have been selected in WR11, and
before the receiver and transmitter are enabled. When ini-
tializing the DPLL, the clock source should be selected
first, followed by the selection of the operating mode.
To avoid metastable problems in the counter, the clock
source selection should be made only while DPLL is dis-
abled, since arbitrarily narrow pulses can be generated at
the output of the multiplexer when it changes status.
The DPLL is enabled by issuing the Enter Search Mode
command in WR14; that is WR14 (7-5) = 001. The Enter
Search Mode command unlocks the counter, which is held
while the DPLL is disabled, and enables the edge detector.
If the DPLL is already enabled when this command is is-
sued, the DPLL also enters Search Mode.
Enter Search Mode is also used to reset the DPLL to a
known state if it is suspected that synchronization has
been lost. Note that the DPLL and the receiver are inde-
3-6
RxD
WR14 (7-5) = 100
WR14 (7-5) = 101
Edge Detector
BRG Clock Source
/RTxC Pin Clock Source
Figure 3-4. Digital Phase Lock Loop
Count Modifier
5-Bit Counter
Figure 3-4 shows a block diagram of the digital phase-
locked loop. It consists of a 5-bit counter, an edge detector,
and a pair of output decoders. The clock for the DPLL
comes from the output of a two-input multiplexer, and the
two outputs go to the transmitter and receive clock
multiplexers. The DPLL is controlled by the seven
commands that are encoded in bits D7, D6 and D5 of
WR14.
pendent, so whether the receiver is disabled or not en-
abled, DPLL will sample whatever is on the RxD line.
DPLL requires a transition in every bit cell, and if this tran-
sition is not present in two consecutively sampled bit cells,
the DPLL will automatically enter search mode and the
DPLL will not provide any clock output.
In Search mode, the counter is held at a specific count and
no outputs are provided. The DPLL remains in this status
until an edge is detected in the receive data stream. This
first edge is assumed to occur on a bit cell boundary, and
the DPLL will begin providing an output to the receiver that
will properly sample the data. From this point on the DPLL
will adjust its output to remain in phase with the receive da-
ta. If the first edge that the DPLL sees does not occur on a
bit cell boundary, the DPLL will eventually lock on to the re-
ceive data, but it will take longer to do so.
The DPLL may be programmed to operate in either of two
modes, as selected by command in WR14.
Note that a channel or hardware reset disables the DPLL,
selects the /RTxC pin as the clock source for the DPLL,
and places it in the NRZI mode.
As in the case of the clock source selection, the mode of
operation should only be changed while the DPLL is dis-
abled to prevent unpredictable results.
WR14 (7-5) = 111 for NRZI mode and
WR14 (7-5) = 110 for FM mode
Decode
Decode
UM011001-0601
Receive
Clock
Transmit
Clock