Z16C3516VSG Zilog, Z16C3516VSG Datasheet - Page 79

• Manufacturer Part Number: Z16C3516VSG
• Description: IC 16MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3516VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4690-5; Z16C3516VSG

UM011001-0601
Bit combination 010 is the Reset Clock Missing Command.
Issuing this command disables the DPLL, resets the clock
missing latches in RR10, and forces a continuous Search
mode state.
Bit combination 001 is the Disable DPLL Command. Issu-
ing this command disables the DPLL, resets the clock
missing latches in RR10, and forces a continuous Search
mode state.
Bit combination 100 is the Set Source = BR Gen Com-
mand. Issuing this command forces the clock for the DPLL
to come from the output of the baud rate generator.
Bit combination 101 is the Set Source = /RTxC Command.
Issuing the command forces the clock for the DPLL to
come from the /RTxC pin or the crystal oscillator, depend-
ing on the state of the XTAL/NO XTAL bit in WR11. This
mode is selected by a channel or hardware reset.
Bit combination 110 is the Set FM Mode Command. This
command forces the DPLL to operate in the FM mode and
is used to recover the clock from FM or Manchester-en-
coded data. (Manchester is decoded by placing the receiv-
er in NRZ mode while the DPLL is in FM mode.)
Bit combination 111 is the Set NRZI Mode Command. Is-
suing this command forces the DPLL to operate in the
NRZI mode. This mode is also selected by a hardware or
channel reset.
Bit 4 is the Local Loopback select bit
Setting this bit to “1” selects the Local Loopback mode of
operation. In this mode, the internal transmitted data is
routed back to the receiver, as well as to the TxD pin. The
/CTS and /DCD inputs are ignored as enables in Local
Loopback mode, even if auto enables is selected. (If so
programmed, transitions on these inputs still cause inter-
rupts.) This mode works with any Transmit/Receive mode
except Loop mode. For meaningful results, the frequency
of the transmit and receive clocks must be the same. This
bit is reset by a channel or hardware reset.
Bit 3 is the Auto Echo select bit
Setting this bit to “1” selects the Auto Echo mode of oper-
ation. In this mode, the TxD pin is connected to RxD, as in
Local Loopback mode, but the receiver still listens to the
RxD input. Transmitted data is never seen inside or out-
side the ISCC in this mode, and /CTS is ignored as a trans-
mit enable. This bit is reset by a channel or hardware reset.
P R E L I M I N A R Y
Bit 2 is the DTR/Request Function select bit
This bit selects the function of the /DTR//REQ pin. If this
is set to “0,” the /DTR//REQ pin follows the state of the
DTR bit in WR5. If this bit is set to “1,” the /DTR//REQ pin
goes Low whenever the transmit buffer becomes empty
and in any of the synchronous modes when CRC has
been sent at the end of a message. The /DTR//REQ does
not go inactive until the internal operation satisfying the
request is complete, which occurs three to four PCLK cy-
cles after the falling edge of /DS, /READ or /WRITE. This
bit is reset by a channel or hardware reset. Note that the
/REQUEST function of this pin is not related to the opera-
tion of the ISCC DMA cell. Since a DMA function is
present on this device, the /REQUEST function would not
normally be used.
Bit 1 is the Baud Rate Generator Source select bit
This bit selects the source of the clock for the baud rate
generator. If this bit is set to “0.” The baud rate generator
clock comes from either the /RTxC pin or the XTAL oscil-
lator (depending on the state of the XTAL/NO XTAL bit). If
this bit is set to “1,” the clock for the baud rate generator is
the ISCC’s PCLK input. Hardware reset sets this bit to “0,”
selecting the /RTxC pin as the clock source for the baud
rate generator.
Bit 0 is the Baud Rate Generator Enable
This bit controls the operation of the baud rate generator.
The counter in the baud rate generator is enabled for
counting when this bit is set to “1,” and counting is inhibited
when this bit is set to “0.” When this bit is set to “1,” change
in the state of this bit is not reflected by the output of the
baud rate generator for two counts of the counter. This al-
lows the command to be synchronized. However, when
set to “0,” disabling is immediate. This bit is reset by a
hardware reset.
5.4.16 Write Register 15 (External/Status
Interrupt Control)
WR15 is the External/Status Source Control register. If the
External/Status interrupts are enabled as a group via
WR1, bits in this register control which External/Status
conditions can cause an interrupt. Only the External/Sta-
tus conditions that occur after the controlling bit are sent to
“1” will cause an interrupt. This is true, even if an Exter-
nal/Status condition is pending at the time the bit is set. Bit
positions for WR15 are shown in Figure 5-17.
Z16C35ISCC™ User’s Manual
Register Descriptions
5-19
5