Z16C3516VSG Zilog, Z16C3516VSG Datasheet - Page 59

• Manufacturer Part Number: Z16C3516VSG
• Description: IC 16MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3516VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4690-5; Z16C3516VSG

UM011001-0601
WR5. At this point the other registers should be initialized
as necessary, as shown in Table 4-14..
Then the Loop Mode bit (D1) in WR10 should be set to “1”.
When all of this is complete the transmitter may be en-
abled by setting bit D3 of WR5 to “1”. Now that the trans-
mitter is enabled, the CRC generator may be initialized by
issuing the Reset Tx CRC Generator command in WR0.
The receiver is enabled by setting the Go Active on Poll bit
(D4) in WR10 to “1”. The ISCC will go on the loop when
seven consecutive “1s” are received, and will signal this by
setting the On Loop bit in RR10. Note that the seven con-
secutive “1s” will set the Break/Abort and Hunt bits in RR0
also. Once the ISCC is on the loop, the Go Active on Poll
bit should be set to “0” until a message is to be transmitted
on the loop. To transmit a message on the loop, the Go Ac-
tive on Poll bit should be set to “1”. At this point the proces-
sor may either write the first character to the transmit buffer
and wait for a transmit buffer empty condition, or wait for
the Break/Abort and Hunt bits to be set in RR10 and the
Loop Sending bit to be set in RR10 before writing the first
data to the transmitter. The Go Active On Poll bit should be
set to “0” after the transmission of the frame has begun. To
go off of the loop, the processor should set the Go Active
On Poll bit in WR10 to “0” and then wait for the Loop Send-
ing bit in RR10 to be set to “0”. At this point the Loop Mode
bit (D1) in WR10 is set to “0” to request an orderly exit from
the loop. The ISCC will exit SDLC Loop mode when seven
consecutive “1s” have been received; at the same time the
Break/Abort and Hunt bits in RR0 will be set to “1”, and the
On Loop bit in RR10 will be set to “0”.
Register
WR4
WR10
WR7
WR3
WR5
WR4
WR6
WR10
Table 4-14. SDLC Loop Mode initialization
Bit No
5-4
7-6
6-5
1-0
7-6
0-7
6-5
7
3
1
2
5
4
2
7
1
Select SDLC mode
Select CRC preset value
Select mark/flag idle bit
Flag
Select bits per character for
receiver
Sync character load inhibit
Address search mode
Description
Auto enables
Select bits per character for
transmitter
Send break
Select SDLC CRC
Select parity
Select clock mode
Address
Select data encoding
4.4.4 SDLC Loop Mode Receive
SDLC Loop mode is quite similar to SDLC mode except
that two additional control bits are used. They are the Loop
Mode bit (D1) and the Go Active on Poll bit (D4) in WR10.
In addition to these two extra control bits, there are also
two status bits in RR10. They are the On Loop bit (D1) and
the Loop Sending bit (D4).
Before Loop mode is selected both the receiver and trans-
mitter must be completely initialized for SDLC operation.
Once this is done, Loop mode is selected by setting bit D1
of WR10 to “1”. At this point the ISCC connects TxD to
RxD with only gate delays in the path. At the same time a
flag is loaded into the Transmit Shift register, and is shifted
to the end of the zero inserter, ready for transmission. The
ISCC will remain in this state until the Go Active on Poll bit
(D4) in WR10 is set to “1”. When this bit is set to “1” the re-
ceiver begins looking for a sequence of seven consecutive
“1s”, indicating either an EOP or an idle line. When the re-
ceiver detects this condition the Break/Abort bit in RR0 is
set to “1” and a one-bit time delay is inserted in the path
from RxD to TxD. The On Loop bit in RR10 is also set to
“1” at this time, and the receiver enters the Hunt mode. The
ISCC cannot transmit on the loop until a flag is received,
causing the receiver to leave Hunt mode, and another
EOP (bit pattern “11111110”) is received. The ISCC is now
on the loop and capable of transmitting on the loop. As
soon as this status is recognized by the processor, the Go
Active On Poll bit in WR10 should be set to “0” to prevent
the ISCC from transmitting on the loop without the consent
of the processor.
4.4.5 SDLC Loop Mode Transmit
To transmit a message on the loop, the Go Active On Poll
bit in WR10 must be set to “1”. Once this is done, the ISCC
will change the next received EOP into a Flag and begin
transmitting on the loop.
When the EOP is received, the Break/Abort and Hunt bits
in RR0 will be set to “1”, and the Loop Sending bit in RR10
will also be set to “1”. Data to be transmitted may be written
after the Go Active On Poll bit has been set or after the re-
ceiver enters Hunt mode.
If the data is written immediately after the Go Active On
Poll bit has been set, the ISCC will only insert one flag after
the EOP is changed into a flag. If the data is not written un-
til after the receiver enters the Hunt mode, the flags will be
transmitted until the data is written. If only one frame is to
be transmitted on the loop in response to an EOP, the pro-
cessor must set the Go Active on Poll bit to “0” before the
last data is written to the transmitter. In this case the trans-
mitter will close the frame with a single flag, and then revert
to the one-bit delay. The Loop Sending bit in RR10 is set
to “0” when the closing Flag has been sent. If more than
one frame is to be transmitted, the Go Active On Poll bit
Z16C35ISCC™ User’s Manual
Data Communication Modes
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