Z16C3516VSG Zilog, Z16C3516VSG Datasheet - Page 9

• Manufacturer Part Number: Z16C3516VSG
• Description: IC 16MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3516VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4690-5; Z16C3516VSG

UM011001-0601
(regardless of character boundaries). In SDLC mode, the
pins act as outputs and are valid on receipt of a flag. The
output is active for one receive clock period (refer to Chap-
ter 4).
TxDA, TxDB. Transmit Data (outputs, active high). These
output signals transmit serial data at standard TTL levels.
/TRxCA, /TRxCB. Transmit/Receive Clocks (inputs or out-
puts, active Low). These pins can be programmed in sev-
eral different modes of operation. /TRxC may supply the
receive clock or the transmit clock in the input mode or
supply the output of the Digital Phase-Locked Loop, the
crystal oscillator, the baud rate generator, or the transmit
clock in the output mode.
/CE. Chip Enable (input, active Low). This signal selects
the ISCC for a peripheral read or write operation. This sig-
nal is ignored when the ISCC is bus master.
AD15-AD0. Data bus (bidirectional, tri-state). These lines
carry data and commands to and from the ISCC.
/RD. Read (bidirectional, active Low). When the ISCC is a
peripheral (i.e., bus slave), this signal indicates a read op-
eration and when the ISCC is selected, enables the ISCC’s
bus drivers. As an input, /RD indicates that the CPU wants
to read from the ISCC read registers. During the Interrupt
Acknowledge cycle, /RD gates the interrupt vector onto the
bus if the ISCC is the highest priority device requesting an
interrupt. When the ISCC is the bus master, this signal is
used to read data. As an output, after the ISCC has taken
control of the system buses, /RD indicates a DMA-con-
trolled read from a memory or I/O port address.
/WR. Write (bidirectional, active Low). When the ISCC is
selected, this signal indicates a write operation. As an in-
put, this indicates that the CPU wants to write control or
command bytes to the ISCC write registers. As an output,
after the ISCC has taken control of the system buses /WR
indicates a DMA-controlled write to a memory or I/O port
address.
/DS. Data Strobe (bidirectional, active Low). A Low on this
signal indicates that the AD15-AD0 bus is used for data
transfer. When the ISCC is not in control of the system bus
and the external system is transferring information to or
from the ISCC, /DS is a timing input used by the ISCC to
move data to or from the AD15-AD0 bus. Data is written
into the ISCC by the external system on the High to Low
/DS transition. Data is read from the ISCC by the external
system while /DS is Low. There are no timing requirements
between /DS as an input and ISCC clock; this allows use
of the ISCC with a system bus which does not have a
bussed clock.
During a DMA operation when the ISCC is in control of the
system, /DS is an output generated by the ISCC and used
by the system to move data to or from the AD15-AD0 bus.
When the ISCC has bus control, it writes to the external
system by placing data on the AD15-AD0 bus before the
High-to-Low /DS transition and holds the data stable until
after the Low-to-High /DS transition; while reading from the
external system, the Low-to-High transition of /DS inputs
data from the AD15-AD0 bus into the ISCC.
R//W. Read/Write (bidirectional). Read polarity is High and
write polarity is Low. When the ISCC is not in control of the
system bus and the external system is transferring infor-
mation to or from the ISCC, R//W is a status input used by
the ISCC to determine if data is entering or leaving on the
AD15-AD0 bus during /DS time. In such a case, Read
(High) indicates that the system is requesting data from the
ISCC and Write (Low) indicates that the system is present-
ing data to the ISCC. The only timing requirements for
R//W as an input are defined relative to /DS. When the
ISCC is in control of the system bus, R//W is an output
generated by the ISCC, with Read (high) indicating that
data is being requested from the addressed location or de-
vice, and Write (low) indicating that data is being present-
ed to the addressed location or device.
/UAS. Upper Address Strobe (Output, active Low). This
signal is used if the output address is more than 16-bit. The
upper address, A31-A16, can be latched externally by the
rising edge of this signal. /UAS is active first before /AS be-
comes active. This signal and /AS are used by the DMA
cell.
/AS. Lower Address Strobe (bidirectional, active Low).
When the ISCC is bus master, this signal is an output, and
is used as a lower address strobe for AD15-AD0. It is used
in conjunction with /UAS since the address is 32-bits. This
signal and /UAS are used by the DMA cell when it is bus
master. When ISCC is not bus master, this signal is used
in the multiplexed bus modes to latch the address on the
AD lines. The /AS signal is not used in the non-multiplexed
bus modes and should be tied to V
these cases.
/WAIT//RDY. Wait/Ready (bidirectional, active Low). This
signal may be programmed to function either as a Wait sig-
nal or Ready signal during the BCR write. When the BCR
is written to Channel A (A1/A//B High during the BCR
write), this signal functions as a /WAIT and thus supports
the READY function of 8X86 microprocessors family.
When the BCR writes to Channel B (A1/A//B Low), this sig-
nal functions as a /READY and supports the /DTACK func-
tion of the 680X0 microprocessor family.
This signal is an output when the ISCC in not bus master.
In this case, the /Wait//RDY signal indicates when the data
is available during a read cycle; when the device is ready
to receive data during a write cycle; and when a valid vec-
tor is available during an interrupt acknowledge cycle.
Z16C35 ISCC™ User’s Manual
CC
General Description
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