PIC18F26K80-I/ML Microchip Technology Inc., PIC18F26K80-I/ML Datasheet - Page 143
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PIC18F26K80-I/ML
Manufacturer Part Number
PIC18F26K80-I/ML
Description
28 QFN-S 6X6MM TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F46K80-IPT.pdf
(628 pages)
Specifications of PIC18F26K80-I/ML
A/d Inputs
8-Channel, 12-Bit
Comparators
2
Cpu Speed
16 MIPS
Eeprom Memory
256 Bytes
Input Output
24
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin QFN
Programmable Memory
64K Bytes
Ram Size
3.6K Bytes
Speed
64 MHz
Temperature Range
–40 to 125 °C
Timers
2-8-bit, 3-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
- Current page: 143 of 628
- Download datasheet (6Mb)
EXAMPLE 7-3:
7.5.2
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
7.5.3
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and repro-
grammed if needed. If the write operation is interrupted
by a MCLR Reset or a WDT Time-out Reset during
normal operation, the user can check the WRERR bit
and rewrite the location(s) as needed.
TABLE 7-2:
2011 Microchip Technology Inc.
TBLPTRU
TBPLTRH
TBLPTRL
TABLAT
INTCON
EECON2
EECON1
IPR4
PIR4
PIE4
Legend: — = unimplemented, read as ‘ 0 ’. Shaded cells are not used during Flash/EEPROM access.
Note 1:
PROGRAM_MEMORY
Name
Required
Sequence
Bit 21 of the TBLPTRU allows access to the device Configuration bits.
WRITE VERIFY
UNEXPECTED TERMINATION OF
WRITE OPERATION
Program Memory Table Pointer High Byte (TBLPTR<15:8>)
Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
Program Memory Table Latch
EEPROM Control Register 2 (not a physical register)
GIE/GIEH
TMR4IP
TMR4IF
TMR4IE
EEPGD
Bit 7
REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
—
BSF
BCF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
BCF
WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
PEIE/GIEL TMR0IE
EECON1, EEPGD
EECON1, CFGS
EECON1, WREN
INTCON, GIE
55h
EECON2
0AAh
EECON2
EECON1, WR
INTCON, GIE
EECON1, WREN
CFGS
EEIP
EEIE
Bit 6
EEIF
—
CMP2IP
CMP2IF
CMP2IE
bit 21
Bit 5
—
(1)
Preliminary
; point to Flash program memory
; access Flash program memory
; enable write to memory
; disable interrupts
; write 55h
; write 0AAh
; start program (CPU stall)
; re-enable interrupts
; disable write to memory
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
CMP1IP
CMP1IE
CMP1IF
INT0IE
FREE
Bit 4
PIC18F66K80 FAMILY
7.5.4
To protect against spurious writes to Flash program
memory, the write initiate sequence must also be
followed. See
CPU”
7.6
See
Protection”
program memory.
WRERR
RBIE
Bit 3
Section 28.6 “Program Verification and Code
—
—
—
for more detail.
Flash Program Operation During
Code Protection
PROTECTION AGAINST
SPURIOUS WRITES
for details on code protection of Flash
Section 28.0 “Special Features of the
TMR0IF
CCP5IP
CCP5IF
CCP5IE
WREN
Bit 2
CCP4IP
CCP4IF
CCP4IE
INT0IF
Bit 1
WR
DS39977C-page 143
CCP3IP
CCP3IF
CCP3IE
Bit 0
RBIF
RD
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