PIC18F26K80-I/ML Microchip Technology Inc., PIC18F26K80-I/ML Datasheet - Page 174
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PIC18F26K80-I/ML
Manufacturer Part Number
PIC18F26K80-I/ML
Description
28 QFN-S 6X6MM TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F46K80-IPT.pdf
(628 pages)
Specifications of PIC18F26K80-I/ML
A/d Inputs
8-Channel, 12-Bit
Comparators
2
Cpu Speed
16 MIPS
Eeprom Memory
256 Bytes
Input Output
24
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin QFN
Programmable Memory
64K Bytes
Ram Size
3.6K Bytes
Speed
64 MHz
Temperature Range
–40 to 125 °C
Timers
2-8-bit, 3-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
- Current page: 174 of 628
- Download datasheet (6Mb)
PIC18F66K80 FAMILY
10.6
External interrupts on the RB0/INT0, RB1/INT1,
RB2/INT2 and RB3/INT3 pins are edge-triggered. If the
corresponding INTEDGx bit in the INTCON2 register is
set (= 1 ), the interrupt is triggered by a rising edge. If
that bit is clear, the trigger is on the falling edge.
When a valid edge appears on the RBx/INTx pin, the
corresponding flag bit, INTxIF, is set. This interrupt can
be disabled by clearing the corresponding enable bit,
INTxIE. Before re-enabling the interrupt, the flag bit
(INTxIF) must be cleared in software in the Interrupt
Service Routine.
All external interrupts (INT0, INT1, INT2 and INT3) can
wake up the processor from the power-managed
modes, if bit, INTxIE, was set prior to going into the
power-managed modes. If the Global Interrupt Enable
bit (GIE) is set, the processor will branch to the interrupt
vector following wake-up.
The interrupt priority for INT1, INT2 and INT3 is
determined by the value contained in the Interrupt
Priority
(INTCON3<7>) and INT3IP (INTCON2<1>).
There is no priority bit associated with INT0. It is always
a high-priority interrupt source.
REGISTER 10-20: IOCB: INTERRUPT-ON-CHANGE PORTB CONTROL REGISTER
DS39977C-page 174
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-4
bit 3-0
Note 1:
IOCB7
R/W-0
INTx Pin Interrupts
bits,
(1)
Interrupt-on-change also requires that the RBIE bit of the INTCON register be set.
IOCB<7:4>: Interrupt-on-Change PORTB Control bits
1 = Interrupt-on-change enabled
0 = Interrupt-on-change disabled
Unimplemented: Read as ‘ 0 ’
INT1IP
IOCB6
R/W-0
(1)
(INTCON3<6>),
W = Writable bit
‘1’ = Bit is set
IOCB5
R/W-0
(1)
INT2IP
IOCB4
R/W-0
Preliminary
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
register (FFh 00h) will set flag bit, TMR0IF. In 16-bit
10.7
In 8-bit mode (the default), an overflow in the TMR0
mode, an overflow in the TMR0H:TMR0L register pair
(FFFFh 0000h) will set TMR0IF.
The interrupt can be enabled/disabled by setting/clearing
enable bit, TMR0IE (INTCON<5>). Interrupt priority for
Timer0 is determined by the value contained in the inter-
rupt priority bit, TMR0IP (INTCON2<2>). For further
details on the Timer0 module, see
Module”
10.8
An input change on PORTB<7:4> sets flag bit, RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit, RBIE (INTCON<3>), and
each individual pin can be enabled/disabled by its
corresponding bit in the IOCB register.
Interrupt priority for PORTB interrupt-on-change is
determined by the value contained in the interrupt
priority bit, RBIP (INTCON2<0>).
U-0
—
(1)
.
TMR0 Interrupt
PORTB Interrupt-on-Change
U-0
—
2011 Microchip Technology Inc.
x = Bit is unknown
U-0
—
Section 13.0 “Timer0
U-0
—
bit 0
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