PIC18F26K80-I/ML Microchip Technology Inc., PIC18F26K80-I/ML Datasheet - Page 508
![no-image](/images/manufacturer_photos/0/4/440/microchip_technology_inc__sml.jpg)
PIC18F26K80-I/ML
Manufacturer Part Number
PIC18F26K80-I/ML
Description
28 QFN-S 6X6MM TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F46K80-IPT.pdf
(628 pages)
Specifications of PIC18F26K80-I/ML
A/d Inputs
8-Channel, 12-Bit
Comparators
2
Cpu Speed
16 MIPS
Eeprom Memory
256 Bytes
Input Output
24
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin QFN
Programmable Memory
64K Bytes
Ram Size
3.6K Bytes
Speed
64 MHz
Temperature Range
–40 to 125 °C
Timers
2-8-bit, 3-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
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PIC18F66K80 FAMILY
GOTO
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
Description:
Words:
Cycles:
Example:
DS39977C-page 508
Q Cycle Activity:
After Instruction
operation
Decode
PC =
No
Q1
Read literal
Address (THERE)
operation
‘k’<7:0>,
Unconditional Branch
GOTO k
0 k 1048575
k PC<20:1>
None
GOTO allows an unconditional branch
anywhere within entire 2-Mbyte memory
range. The 20-bit value ‘k’ is loaded into
PC<20:1>. GOTO is always a two-cycle
instruction.
2
2
GOTO THERE
1110
1111
No
Q2
k
1111
19
operation
operation
kkk
No
No
Q3
k
kkkk
7
kkk
Read literal
Write to PC
‘k’<19:8>,
operation
No
Q4
kkkk
kkkk
Preliminary
0
8
INCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
CNT
Z
C
DC
CNT
Z
C
DC
Q1
=
=
=
=
=
=
=
=
register ‘f’
Increment f
INCF
0 f 255
d [0,1]
a [0,1]
(f) + 1 dest
The contents of register ‘f’ are
incremented. If ‘d’ is ‘ 0 ’, the result is
placed in W. If ‘d’ is ‘ 1 ’, the result is
placed back in register ‘f’ (default).
If ‘a’ is ‘ 0 ’, the Access Bank is selected.
If ‘a’ is ‘ 1 ’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘ 0 ’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 29.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode”
1
1
INCF
C, DC, N, OV, Z
Read
0010
Q2
FFh
0
?
?
00h
1
1
1
2011 Microchip Technology Inc.
f {,d {,a}}
10da
CNT, 1, 0
Process
Data
Q3
ffff
for details.
destination
Write to
Q4
ffff
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