PIC18F26K80-I/ML Microchip Technology Inc., PIC18F26K80-I/ML Datasheet - Page 440
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PIC18F26K80-I/ML
Manufacturer Part Number
PIC18F26K80-I/ML
Description
28 QFN-S 6X6MM TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F46K80-IPT.pdf
(628 pages)
Specifications of PIC18F26K80-I/ML
A/d Inputs
8-Channel, 12-Bit
Comparators
2
Cpu Speed
16 MIPS
Eeprom Memory
256 Bytes
Input Output
24
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin QFN
Programmable Memory
64K Bytes
Ram Size
3.6K Bytes
Speed
64 MHz
Temperature Range
–40 to 125 °C
Timers
2-8-bit, 3-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
- Current page: 440 of 628
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PIC18F66K80 FAMILY
REGISTER 27-58: IPR5: PERIPHERAL INTERRUPT PRIORITY REGISTER 5
DS39977C-page 440
Mode 0
Mode 1,2
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
In CAN Mode 1 and 2, these bits are forced to ‘ 0 ’.
bit 7
IRXIP: CAN Bus Error Message Received Interrupt Priority bi t
1 = High priority
0 = Low priority
WAKIP: CAN Bus Activity Wake-up Interrupt Priority bit
1 = High priority
0 = Low priority
ERRIP: CAN Module Error Interrupt Priority bit
1 = High priority
0 = Low priority
When CAN is in Mode 0:
TXB2IP: CAN Transmit Buffer 2 Interrupt Priority bit
1 = High priority
0 = Low priority
When CAN is in Mode 1 or 2:
TXBnIP: CAN Transmit Buffer Interrupt Priority bit
1 = High priority
0 = Low priority
TXB1IP: CAN Transmit Buffer 1 Interrupt Priority bit
1 = High priority
0 = Low priority
TXB0IP: CAN Transmit Buffer 0 Interrupt Priority bit
1 = High priority
0 = Low priority
When CAN is in Mode 0:
RXB1IP: CAN Receive Buffer 1 Interrupt Priority bit
1 = High priority
0 = Low priority
When CAN is in Mode 1 or 2:
RXBnIP: CAN Receive Buffer Interrupts Priority bit
1 = High priority
0 = Low priority
When CAN is in Mode 0:
RXB0IP: CAN Receive Buffer 0 Interrupt Priority bit
1 = High priority
0 = Low priority
When CAN is in Mode 1:
Unimplemented: Read as ‘ 0 ’
When CAN is in Mode 2:
FIFOWMIP: FIFO Watermark Interrupt Priority bit
1 = High priority
0 = Low priority
R/W-x
R/W-x
IRXIP
IRXIP
WAKIP
WAKIP
R/W-x
R/W-x
W = Writable bit
‘1’ = Bit is set
ERRIP
ERRIP
R/W-x
R/W-x
Preliminary
TXB2IP
TXBnIP
R/W-x
R/W-x
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
(1)
(1)
TXB1IP
TXB1IP
R/W-x
R/W-x
(1)
(1)
TXB0IP
TXB0IP
R/W-x
R/W-x
(1)
(1)
2011 Microchip Technology Inc.
x = Bit is unknown
RXB1IP
RXBnIP
R/W-x
R/W-x
FIFOWMIP
RXB0IP
R/W-x
R/W-x
bit 0
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