PIC18F26K80-I/ML Microchip Technology Inc., PIC18F26K80-I/ML Datasheet - Page 507
![no-image](/images/manufacturer_photos/0/4/440/microchip_technology_inc__sml.jpg)
PIC18F26K80-I/ML
Manufacturer Part Number
PIC18F26K80-I/ML
Description
28 QFN-S 6X6MM TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F46K80-IPT.pdf
(628 pages)
Specifications of PIC18F26K80-I/ML
A/d Inputs
8-Channel, 12-Bit
Comparators
2
Cpu Speed
16 MIPS
Eeprom Memory
256 Bytes
Input Output
24
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin QFN
Programmable Memory
64K Bytes
Ram Size
3.6K Bytes
Speed
64 MHz
Temperature Range
–40 to 125 °C
Timers
2-8-bit, 3-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
- Current page: 507 of 628
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DECFSZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
2011 Microchip Technology Inc.
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
No
No
No
PC
CNT
If CNT
If CNT
Q1
Q1
Q1
PC =
PC =
=
=
=
register ‘f’
operation
operation
operation
Decrement f, Skip if 0
DECFSZ f {,d {,a}}
0 f 255
d [0,1]
a [0,1]
(f) – 1 dest,
skip if result = 0
None
The contents of register ‘f’ are
decremented. If ‘d’ is ‘ 0 ’, the result is
placed in W. If ‘d’ is ‘ 1 ’, the result is
placed back in register ‘f’ (default).
If the result is ‘ 0 ’, the next instruction
which is already fetched is discarded
and a NOP is executed instead, making
it a two-cycle instruction.
If ‘a’ is ‘ 0 ’, the Access Bank is selected.
If ‘a’ is ‘ 1 ’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘ 0 ’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 29.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode”
1
1(2)
Note: 3 cycles if skip and followed
HERE
CONTINUE
Read
0010
No
No
No
Q2
Q2
Q2
Address (HERE)
CNT – 1
0 ;
Address (CONTINUE)
0 ;
Address (HERE + 2)
by a 2-word instruction.
11da
operation
operation
operation
DECFSZ
GOTO
Process
Data
No
No
No
Q3
Q3
Q3
ffff
for details.
CNT, 1, 1
LOOP
destination
operation
operation
operation
Write to
No
No
No
Q4
Q4
Q4
ffff
Preliminary
PIC18F66K80 FAMILY
DCFSNZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
No
No
No
TEMP
TEMP
If TEMP
If TEMP
Q1
Q1
Q1
PC
PC
register ‘f’
operation
operation
operation
Decrement f, Skip if Not 0
DCFSNZ
0 f 255
d [0,1]
a [0,1]
(f) – 1 dest,
skip if result 0
None
The contents of register ‘f’ are
decremented. If ‘d’ is ‘ 0 ’, the result is
placed in W. If ‘d’ is ‘ 1 ’, the result is
placed back in register ‘f’ (default).
If the result is not ‘ 0 ’, the next
instruction which is already fetched is
discarded and a NOP is executed
instead, making it a two-cycle
instruction.
If ‘a’ is ‘ 0 ’, the Access Bank is selected.
If ‘a’ is ‘ 1 ’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘ 0 ’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 29.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode”
1
1(2)
Note:
HERE
ZERO
NZERO
Read
0100
No
No
No
Q2
Q2
Q2
3 cycles if skip and followed
by a 2-word instruction.
=
=
=
=
=
DCFSNZ
:
:
f {,d {,a}}
11da
operation
operation
operation
?
TEMP – 1,
0 ;
Address (ZERO)
0 ;
Address (NZERO)
Process
Data
No
No
No
Q3
Q3
Q3
DS39977C-page 507
TEMP, 1, 0
ffff
for details.
destination
operation
operation
operation
Write to
No
No
No
Q4
Q4
Q4
ffff
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