PIC18F26K80-I/ML Microchip Technology Inc., PIC18F26K80-I/ML Datasheet - Page 339
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PIC18F26K80-I/ML
Manufacturer Part Number
PIC18F26K80-I/ML
Description
28 QFN-S 6X6MM TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F46K80-IPT.pdf
(628 pages)
Specifications of PIC18F26K80-I/ML
A/d Inputs
8-Channel, 12-Bit
Comparators
2
Cpu Speed
16 MIPS
Eeprom Memory
256 Bytes
Input Output
24
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin QFN
Programmable Memory
64K Bytes
Ram Size
3.6K Bytes
Speed
64 MHz
Temperature Range
–40 to 125 °C
Timers
2-8-bit, 3-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
- Current page: 339 of 628
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22.0
The Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART) module is one of two
serial I/O modules. (Generically, the EUSART is also
known as a Serial Communications Interface or SCI.)
The EUSART can be configured as a full-duplex,
asynchronous system that can communicate with
peripheral devices, such as CRT terminals and
personal computers. It can also be configured as a
half-duplex synchronous system that can communicate
with peripheral devices, such as A/D or D/A integrated
circuits, serial EEPROMs, etc.
The Enhanced USART module implements additional
features, including automatic baud rate detection and
calibration, automatic wake-up on Sync Break recep-
tion and 12-bit Break character transmit. These make it
ideally suited for use in Local Interconnect Network bus
(LIN/J2602 bus) systems.
TABLE 22-1:
In order to configure the pins as an EUSART:
• For EUSART1:
2011 Microchip Technology Inc.
Note 1:
40/44-pin PORTC
- SPEN (RCSTA1<7>) must be set (= 1 )
- TRISx<x> must be set (= 1 )
- For Asynchronous and Synchronous Master
- For Synchronous Slave mode, TRISC<x>
Count
28-pin
64-pin
Pin
modes, TRISx<x> must be cleared (= 0 )
must be set (= 1 )
ENHANCED UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (EUSART)
The EUSART control will automatically reconfigure the pin from input to output as needed.
PORTB
PORTE
Port
CONFIGURING EUSART PINS
RC6/TX1/CK1 and RC7/RX1/DT1
RE7/TX2/CK2 and RE6/RX2/DT2
RB7/PGD/T3G/RX2/DT2/KBI3
RB6/PGC/TX2/CK2/KBI2 and
USART1
Pins
Preliminary
(1)
PORTC
PORTD
PORTG
PIC18F66K80 FAMILY
Port
All members of the PIC18F66K80 family are equipped
with two independent EUSART modules, referred to as
EUSART1 and EUSART2. They can be configured in
the following modes:
• Asynchronous (full duplex) with:
• Synchronous – Master (half duplex) with
• Synchronous – Slave (half duplex) with selectable
The pins of EUSART1 and EUSART2 are multiplexed
with the functions with the following ports, depending
on the device pin count. See
• For EUSART2:
- Auto-wake-up on character reception
- Auto-baud calibration
- 12-bit Break character transmission
selectable clock polarity
clock polarity
- SPEN (RCSTA2<7>) must be set (= 1 )
- TRISx<x> must be set (= 1 )
- For Asynchronous and Synchronous Master
- For Synchronous Slave mode, TRISx<x>
modes, TRISx<x> must be cleared (= 0 )
must be set (= 1 )
RG3/TX1/CK1 and RG0/RX1/DT1
RC6/TX1/CK1 and RC7/RX1/DT1
RD6/TX2/CK2/P1C/PSP6 and
RD7/RX2/DT2/P1D/PSP7
USART2
Pins
Table
22-1.
DS39977C-page 339
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