PIC18F26K80-I/ML Microchip Technology Inc., PIC18F26K80-I/ML Datasheet - Page 197
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PIC18F26K80-I/ML
Manufacturer Part Number
PIC18F26K80-I/ML
Description
28 QFN-S 6X6MM TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F46K80-IPT.pdf
(628 pages)
Specifications of PIC18F26K80-I/ML
A/d Inputs
8-Channel, 12-Bit
Comparators
2
Cpu Speed
16 MIPS
Eeprom Memory
256 Bytes
Input Output
24
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin QFN
Programmable Memory
64K Bytes
Ram Size
3.6K Bytes
Speed
64 MHz
Temperature Range
–40 to 125 °C
Timers
2-8-bit, 3-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
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TABLE 11-13: PORTG FUNCTIONS (CONTINUED)
TABLE 11-14: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG
2011 Microchip Technology Inc.
RG4/T0CKI
Legend:
Note 1:
PORTG
TRISG
PADCFG1
Legend: — = unimplemented, read as ‘ 0 ’. Shaded cells are not used by PORTG.
Note 1:
Pin Name
Name
2:
O = Output, I = Input, ANA = Analog Signal, DIG = CMOS Output, ST = Schmitt Trigger Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)
Alternate pin assignment for T0CKI on 64-pin devices when the T0CKMX Configuration bit is cleared.
Default pin assignment for T3CKI on 64-pin devices when the T3CKMX Configuration bit is set.
Unimplemented on 28-pin devices. Read as ‘ 0 ’.
Function
RDPU
T0CKI
Bit 7
RG4
—
—
(1)
Setting
TRIS
REPU
0
1
x
Bit 6
—
—
I/O
O
I
I
RFPU
I/O Type
Bit 5
—
—
DIG
ST
ST
(1)
Preliminary
LATG<4> data output.
PORTG<4> data input.
Timer0 clock input.
RGPU
TRISG4
Bit 4
RG4
PIC18F66K80 FAMILY
(1)
TRISG3
Bit 3
RG3
—
Description
TRISG2
Bit 2
RG2
—
TRISG1
Bit 1
RG1
—
DS39977C-page 197
CTMUDS
TRISG0
Bit 0
RG0
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