PIC18F26K80-I/ML Microchip Technology Inc., PIC18F26K80-I/ML Datasheet - Page 166
![no-image](/images/manufacturer_photos/0/4/440/microchip_technology_inc__sml.jpg)
PIC18F26K80-I/ML
Manufacturer Part Number
PIC18F26K80-I/ML
Description
28 QFN-S 6X6MM TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F46K80-IPT.pdf
(628 pages)
Specifications of PIC18F26K80-I/ML
A/d Inputs
8-Channel, 12-Bit
Comparators
2
Cpu Speed
16 MIPS
Eeprom Memory
256 Bytes
Input Output
24
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin QFN
Programmable Memory
64K Bytes
Ram Size
3.6K Bytes
Speed
64 MHz
Temperature Range
–40 to 125 °C
Timers
2-8-bit, 3-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
- Current page: 166 of 628
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PIC18F66K80 FAMILY
REGISTER 10-12: PIE4: PERIPHERAL INTERRUPT ENABLE REGISTER 4
DS39977C-page 166
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
TMR4IE
R/W-0
TMR4IE: TMR4 Overflow Interrupt Flag bit
1 = Interrupt enabled
0 = Interrupt disabled
EEIE: Data EEDATA/Flash Write Operation Interrupt Flag bit
1 = Interrupt enabled
0 = Interrupt disabled
CMP2IE: CMP2 Interrupt Flag bit
1 = Interrupt enabled
0 = Interrupt disabled
CMP1IE: CMP1 Interrupt Flag bit
1 = Interrupt enabled
0 = Interrupt disabled
Unimplemented: Read as ‘ 0 ’
CCP5IE: CCP5 Interrupt Flag bit
1 = Interrupt enabled
0 = Interrupt disabled
CCP4IE: CCP4 Interrupt Flag bit
1 = Interrupt enabled
0 = Interrupt disabled
CCP3IE: CCP3 Interrupt Flag bits
1 = Interrupt enabled
0 = Interrupt disabled
R/W-0
EEIE
W = Writable bit
‘1’ = Bit is set
CMP2IE
R/W-0
CMP1IE
R/W-0
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
—
CCP5IE
R/W-0
2011 Microchip Technology Inc.
x = Bit is unknown
CCP4IE
R/W-0
CCP3IE
R/W-0
bit 0
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