PIC18F26K80-I/ML Microchip Technology Inc., PIC18F26K80-I/ML Datasheet - Page 80
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PIC18F26K80-I/ML
Manufacturer Part Number
PIC18F26K80-I/ML
Description
28 QFN-S 6X6MM TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F46K80-IPT.pdf
(628 pages)
Specifications of PIC18F26K80-I/ML
A/d Inputs
8-Channel, 12-Bit
Comparators
2
Cpu Speed
16 MIPS
Eeprom Memory
256 Bytes
Input Output
24
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin QFN
Programmable Memory
64K Bytes
Ram Size
3.6K Bytes
Speed
64 MHz
Temperature Range
–40 to 125 °C
Timers
2-8-bit, 3-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
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PIC18F66K80 FAMILY
TABLE 4-4:
DS39977C-page 80
PRI_IDLE mode
SEC_IDLE mode
RC_IDLE mode
Sleep mode
Note 1:
Power-Managed
2:
3:
4:
5:
T
runs concurrently with any other required delays (see
Includes postscaler derived frequencies. On Reset, INTOSC defaults to HF-INTOSC at 8 MHz.
T
(Parameter F12,
Execution continues during T
The clock source is dependent upon the settings of the SCS (OSCCON<1:0>), IRCF (OSCCON<6:4>)
and FOSC (CONFIG1H<3:0>) bits.
Mode
CSD
OST
(Parameter 38,
is the Oscillator Start-up Timer (Parameter 32,
EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE
(BY CLOCK SOURCES)
Table
Table
31-7); it is also designated as T
Clock Source
31-11) is a required delay when waking from Sleep and all Idle modes, and
MF-INTOSC
MF-INTOSC
MF-INTOSC
HF-INTOSC
HF-INTOSC
HF-INTOSC
IOBST
LF-INTOSC
LF-INTOSC
LF-INTOSC
LP, XT, HS
LP, XT, HS
EC, RC
EC, RC
HSPLL
HSPLL
SOSC
(Parameter 39,
Preliminary
(2)
(2)
(2)
(2)
(2)
(2)
(5)
Table
Table
Section 4.4 “Idle Modes”
PLL
31-11), the INTOSC stabilization period.
.
31-11). T
T
Exit Delay
OST
T
T
T
T
T
T
IOBST
CSD
CSD
CSD
CSD
OST
+ t
RC
(1)
(1)
(1)
(3)
(1)
rc
(4)
(3)
is the PLL Lock-out Timer
2011 Microchip Technology Inc.
).
Clock Ready
Status Bits
SOSCRUN
MFIOFS
MFIOFS
MFIOFS
HFIOFS
HFIOFS
HFIOFS
OSTS
OSTS
None
None
None
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