PIC18F26K80-I/ML Microchip Technology Inc., PIC18F26K80-I/ML Datasheet - Page 415
![no-image](/images/manufacturer_photos/0/4/440/microchip_technology_inc__sml.jpg)
PIC18F26K80-I/ML
Manufacturer Part Number
PIC18F26K80-I/ML
Description
28 QFN-S 6X6MM TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F46K80-IPT.pdf
(628 pages)
Specifications of PIC18F26K80-I/ML
A/d Inputs
8-Channel, 12-Bit
Comparators
2
Cpu Speed
16 MIPS
Eeprom Memory
256 Bytes
Input Output
24
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin QFN
Programmable Memory
64K Bytes
Ram Size
3.6K Bytes
Speed
64 MHz
Temperature Range
–40 to 125 °C
Timers
2-8-bit, 3-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
- Current page: 415 of 628
- Download datasheet (6Mb)
REGISTER 27-19: RXBnDLC: RECEIVE BUFFER ‘n’ DATA LENGTH CODE REGISTERS [0 n 1]
REGISTER 27-20: RXBnDm: RECEIVE BUFFER ‘n’ DATA FIELD BYTE ‘m’ REGISTERS
2011 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3-0
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-0
RXBnDm7
U-0
R-x
—
Unimplemented: Read as ‘ 0 ’
RXRTR: Receiver Remote Transmission Request bit
1 = Remote transfer request
0 = No remote transfer request
RB1: Reserved bit 1
Reserved by CAN Spec and read as ‘ 0 ’.
RB0: Reserved bit 0
Reserved by CAN Spec and read as ‘ 0 ’.
DLC<3:0>: Data Length Code bits
1111 = Invalid
1110 = Invalid
1101 = Invalid
1100 = Invalid
1011 = Invalid
1010 = Invalid
1001 = Invalid
1000 = Data length = 8 bytes
0111 = Data length = 7 bytes
0110 = Data length = 6 bytes
0101 = Data length = 5 bytes
0100 = Data length = 4 bytes
0011 = Data length = 3 bytes
0010 = Data length = 2 bytes
0001 = Data length = 1 byte
0000 = Data length = 0 bytes
RXBnDm<7:0>: Receive Buffer n Data Field Byte m bits (where 0 n < 1 and 0 < m < 7)
Each receive buffer has an array of registers. For example, Receive Buffer 0 has 8 registers: RXB0D0
to RXB0D7.
RXBnDm6
RXRTR
R-x
R-x
[0 n 1, 0 m 7]
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
RXBnDm5
RB1
R-x
R-x
RXBnDm4
R-x
R-x
R0
Preliminary
U = Unimplemented bit, read as ‘0’
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
‘0’ = Bit is cleared
PIC18F66K80 FAMILY
RXBnDm3
DLC3
R-x
R-x
RXBnDm2
DLC2
R-x
R-x
x = Bit is unknown
x = Bit is unknown
RXBnDm1
DLC1
R-x
R-x
DS39977C-page 415
RXBnDm0
DLC0
R-x
R-x
bit 0
bit 0
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