PIC18F26K80-I/ML Microchip Technology Inc., PIC18F26K80-I/ML Datasheet - Page 73
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PIC18F26K80-I/ML
Manufacturer Part Number
PIC18F26K80-I/ML
Description
28 QFN-S 6X6MM TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F46K80-IPT.pdf
(628 pages)
Specifications of PIC18F26K80-I/ML
A/d Inputs
8-Channel, 12-Bit
Comparators
2
Cpu Speed
16 MIPS
Eeprom Memory
256 Bytes
Input Output
24
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin QFN
Programmable Memory
64K Bytes
Ram Size
3.6K Bytes
Speed
64 MHz
Temperature Range
–40 to 125 °C
Timers
2-8-bit, 3-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
- Current page: 73 of 628
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4.4.1
This mode is unique among the three low-power Idle
modes, in that it does not disable the primary device
clock. For timing-sensitive applications, this allows for
the fastest resumption of device operation with its more
accurate, primary clock source, since the clock source
does not have to “warm-up” or transition from another
oscillator.
PRI_IDLE mode is entered from PRI_RUN mode by
setting the IDLEN bit and executing a SLEEP instruc-
tion. If the device is in another Run mode, set IDLEN
first, then clear the SCS bits and execute SLEEP.
Although the CPU is disabled, the peripherals continue
to be clocked from the primary clock source specified
by the FOSC<3:0> Configuration bits. The OSTS bit
remains set (see
When a wake event occurs, the CPU is clocked from the
primary clock source. A delay of interval, T
(Parameter 39,
wake event and the start of code execution. This is
required to allow the CPU to become ready to execute
instructions. After the wake-up, the OSTS bit remains
set. The IDLEN and SCS bits are not affected by the
wake-up (see
FIGURE 4-7:
FIGURE 4-8:
2011 Microchip Technology Inc.
CPU Clock
Peripheral
Program
Counter
CPU Clock
Peripheral
OSC1
Clock
Program
Counter
OSC1
Clock
PRI_IDLE MODE
Figure
Table
Figure
Q1
4-8).
Q1
31-11), is required between the
TRANSITION TIMING FOR ENTRY TO IDLE MODE
TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE
4-7).
Q2
Wake Event
PC
Q3
T
CSD
Q4
CSD
Preliminary
Q1
PIC18F66K80 FAMILY
PC
4.4.2
In SEC_IDLE mode, the CPU is disabled but the
peripherals continue to be clocked from the SOSC
oscillator. This mode is entered from SEC_RUN by set-
ting the IDLEN bit and executing a SLEEP instruction. If
the device is in another Run mode, set the IDLEN bit
first, then set the SCS<1:0> bits to ‘01’ and execute
SLEEP. When the clock source is switched to the SOSC
oscillator, the primary oscillator is shut down, the OSTS
bit is cleared and the SOSCRUN bit is set.
When a wake event occurs, the peripherals continue to
be clocked from the SOSC oscillator. After an interval
of T
executing code that is being clocked by the SOSC
oscillator. The IDLEN and SCS bits are not affected by
the wake-up and the SOSC oscillator continues to run
(see
CSD
Figure
following the wake event, the CPU begins
SEC_IDLE MODE
4-8).
PC + 2
Q2
Q3
DS39977C-page 73
Q4
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